JPS61100154U - - Google Patents

Info

Publication number
JPS61100154U
JPS61100154U JP18457384U JP18457384U JPS61100154U JP S61100154 U JPS61100154 U JP S61100154U JP 18457384 U JP18457384 U JP 18457384U JP 18457384 U JP18457384 U JP 18457384U JP S61100154 U JPS61100154 U JP S61100154U
Authority
JP
Japan
Prior art keywords
integrated circuit
electrode
monolithic integrated
resistor
inductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18457384U
Other languages
Japanese (ja)
Other versions
JPH0412693Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18457384U priority Critical patent/JPH0412693Y2/ja
Publication of JPS61100154U publication Critical patent/JPS61100154U/ja
Application granted granted Critical
Publication of JPH0412693Y2 publication Critical patent/JPH0412693Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Networks Using Active Elements (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例であるモノリシツ
ク重積回路の構成を示す斜視図、第２図は、第１
図のモノリシツク集積回路の等価回路を示す図、
第３図は第２図の等価回路を示す図、第４図及び
第５図は、それぞれ第１図のモノリシツク集積回
路における各部の特性を示す図、第６図は従来の
モノリシツク集積回路の構成を示す斜視図、第７
図は第６図のモノリシツク集積回路の等価回路を
示す図である。 図において、１…半絶縁性基板、１…インダク
タ、３…抵抗体(a)、４，５，６…電極(a)，電極
(b)，電極(c)、７…ＦＥＴ、８…ソース電極、９
…ドレイン電極、１０…ゲート電極、１１，１３
…抵抗体(b)，抵抗体(c)、１２，１４…電極、１
５…並行平板コンデンサ、１６…金属膜である。
なお、各図中、同一符号は同一、又は相当部分を
示す。 FIG. 1 is a perspective view showing the configuration of a monolithic stacking circuit which is an embodiment of this invention, and FIG.
A diagram showing an equivalent circuit of the monolithic integrated circuit shown in FIG.
3 is a diagram showing the equivalent circuit of FIG. 2, FIGS. 4 and 5 are diagrams each showing the characteristics of each part in the monolithic integrated circuit of FIG. 1, and FIG. 6 is the configuration of a conventional monolithic integrated circuit. Perspective view showing 7th
This figure shows an equivalent circuit of the monolithic integrated circuit of FIG. 6. In the figure, 1... Semi-insulating substrate, 1... Inductor, 3... Resistor (a), 4, 5, 6... Electrode (a), Electrode
(b), electrode (c), 7...FET, 8...source electrode, 9
...Drain electrode, 10...Gate electrode, 11, 13
...Resistor (b), resistor (c), 12, 14... Electrode, 1
5...Parallel plate capacitor, 16...Metal film.
In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＧａＡｓなどの半絶縁性基板上にインダクタを
形成したモノリシツク集積回路において、ＦＥＴ
のゲート電極とソース電極との間に抵抗体を設け
、かつ前記ゲート電極とドレイン電極との間に、
ストリツプ導体により形成したインダクタ、イオ
ン注入などにより形成した半導体抵抗、及びこの
半導体抵抗の両端に接続した電極を設けたことを
特徴とするモノリシツク集積回路。 In a monolithic integrated circuit in which an inductor is formed on a semi-insulating substrate such as GaAs, FET
A resistor is provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode,
A monolithic integrated circuit comprising an inductor formed from a strip conductor, a semiconductor resistor formed by ion implantation, and electrodes connected to both ends of the semiconductor resistor.
JP18457384U 1984-12-05 1984-12-05 Expired JPH0412693Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18457384U JPH0412693Y2 (en) 1984-12-05 1984-12-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18457384U JPH0412693Y2 (en) 1984-12-05 1984-12-05

Publications (2)

Publication Number Publication Date
JPS61100154U true JPS61100154U (en) 1986-06-26
JPH0412693Y2 JPH0412693Y2 (en) 1992-03-26

Family

ID=30742059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18457384U Expired JPH0412693Y2 (en) 1984-12-05 1984-12-05

Country Status (1)

Country Link
JP (1) JPH0412693Y2 (en)

Also Published As

Publication number Publication date
JPH0412693Y2 (en) 1992-03-26

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