JPS6349225U - - Google Patents
Info
- Publication number
- JPS6349225U JPS6349225U JP14358586U JP14358586U JPS6349225U JP S6349225 U JPS6349225 U JP S6349225U JP 14358586 U JP14358586 U JP 14358586U JP 14358586 U JP14358586 U JP 14358586U JP S6349225 U JPS6349225 U JP S6349225U
- Authority
- JP
- Japan
- Prior art keywords
- chip capacitor
- electrodes
- metal thin
- dielectric substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 3
- 239000002184 metal Substances 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Amplifiers (AREA)
Description
第１図は本考案のチツプコンデンサを使用した
トランジスタ内部整合回路の一実施例を示す平面
図、第２図は従来のチツプコンデンサを使用した
トランジスタ内部整合回路の一構成例を示す平面
図、第３図は第２図の等価回路図である。
１，１ａ……容器底面、２，２ａ……チツプコ
ンデンサ、３，３ａ……トランジスタ素子、４，
４ａ……入力端子、５，５ａ……出力端子、６，
６ａ，７，７ａ，８，８ａ……導線、９，９ａ…
…表面電極、１０，１１……微小マーク、１２…
…基準用突起。
FIG. 1 is a plan view showing an example of a transistor internal matching circuit using the chip capacitor of the present invention, and FIG. 2 is a plan view showing an example of the configuration of a transistor internal matching circuit using a conventional chip capacitor. FIG. 3 is an equivalent circuit diagram of FIG. 2. 1, 1a... bottom of container, 2, 2a... chip capacitor, 3, 3a... transistor element, 4,
4a...Input terminal, 5, 5a...Output terminal, 6,
6a, 7, 7a, 8, 8a... conductor wire, 9, 9a...
...Surface electrode, 10, 11...Minute mark, 12...
...Reference protrusion.
Claims (1)
面主要部にそれぞれ金属薄膜により電極を形成し
たチツプコンデンサにおいて、前記電極と同じ金
属薄膜で形成された複数個の位置合わせ用微小マ
ークが前記誘電体基板の表面周辺部の前記電極を
挾んで対向する対辺上の線対称な位置に配置され
ていることを特徴とするチツプコンデンサ。 In a chip capacitor in which electrodes are formed using metal thin films on the back surface of a rectangular dielectric substrate and the main surface area excluding the peripheral area, a plurality of minute alignment marks made of the same metal thin film as the electrodes are formed on the dielectric substrate. A chip capacitor characterized in that the chip capacitor is arranged at a line-symmetrical position on opposite sides sandwiching the electrode in the peripheral part of the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14358586U JPS6349225U (en) | 1986-09-18 | 1986-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14358586U JPS6349225U (en) | 1986-09-18 | 1986-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6349225U true JPS6349225U (en) | 1988-04-04 |
Family
ID=31053406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14358586U Pending JPS6349225U (en) | 1986-09-18 | 1986-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6349225U (en) |
-
1986
- 1986-09-18 JP JP14358586U patent/JPS6349225U/ja active Pending