JPS6210451U - - Google Patents

Info

Publication number
JPS6210451U
JPS6210451U JP10199185U JP10199185U JPS6210451U JP S6210451 U JPS6210451 U JP S6210451U JP 10199185 U JP10199185 U JP 10199185U JP 10199185 U JP10199185 U JP 10199185U JP S6210451 U JPS6210451 U JP S6210451U
Authority
JP
Japan
Prior art keywords
semiconductor element
peripheral wall
facing
substrates
element piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10199185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10199185U priority Critical patent/JPS6210451U/ja
Publication of JPS6210451U publication Critical patent/JPS6210451U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Bipolar Transistors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の断面図、第２図は
従来の並列接続トランジスタチツプからなる半導
体装置の基板の平面図、第３図は第２図の半導体
装置の断面図である。 １１，１２：金属基板、２，３：トランジスタ
チツプ、２１，３１：エミツタ突起電極、２２，
３２：ベース突起電極、５：エミツタ端子導体、
６：ベース端子導体、８：容器周壁。 FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a plan view of a substrate of a conventional semiconductor device comprising parallel-connected transistor chips, and FIG. 3 is a sectional view of the semiconductor device of FIG. 2. 11, 12: metal substrate, 2, 3: transistor chip, 21, 31: emitter protrusion electrode, 22,
32: base protrusion electrode, 5: emitter terminal conductor,
6: Base terminal conductor, 8: Container peripheral wall.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一つの容器内に複数の半導体素子片が収容され
、各素子片上の電極が互いに接続されるものにお
いて、間隔を置いて対向する二つの金属基板上に
それぞれ半導体素子片が互いに対向して固着され
、該両基板を周壁で結合する絶縁性周壁を貫通す
る端子導体に各半導体素子片の自由表面上にある
突起電極が接触していることを特徴とする半導体
装置。 In a case where a plurality of semiconductor element pieces are housed in a single container and the electrodes on each element piece are connected to each other, the semiconductor element pieces are fixed facing each other on two metal substrates facing each other at a distance. . A semiconductor device, characterized in that a protruding electrode on the free surface of each semiconductor element piece is in contact with a terminal conductor that penetrates an insulating peripheral wall that connects both substrates by a peripheral wall.
JP10199185U 1985-07-04 1985-07-04 Pending JPS6210451U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10199185U JPS6210451U (en) 1985-07-04 1985-07-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10199185U JPS6210451U (en) 1985-07-04 1985-07-04

Publications (1)

Publication Number Publication Date
JPS6210451U true JPS6210451U (en) 1987-01-22

Family

ID=30973231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10199185U Pending JPS6210451U (en) 1985-07-04 1985-07-04

Country Status (1)

Country Link
JP (1) JPS6210451U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196438A (en) * 1987-10-09 1989-04-14 Mitsubishi Motors Corp O2 sensor fixing structure for internal combustion engine having turbo-charger
JP2002289774A (en) * 2001-03-27 2002-10-04 Furukawa Electric Co Ltd:The Multi-layer structure semiconductor, device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196438A (en) * 1987-10-09 1989-04-14 Mitsubishi Motors Corp O2 sensor fixing structure for internal combustion engine having turbo-charger
JP2002289774A (en) * 2001-03-27 2002-10-04 Furukawa Electric Co Ltd:The Multi-layer structure semiconductor, device

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