JPS609238U - 高集積ハイブリツドｉｃ - Google Patents

高集積ハイブリツドｉｃ

Info

Publication number
JPS609238U
JPS609238U JP1983100914U JP10091483U JPS609238U JP S609238 U JPS609238 U JP S609238U JP 1983100914 U JP1983100914 U JP 1983100914U JP 10091483 U JP10091483 U JP 10091483U JP S609238 U JPS609238 U JP S609238U
Authority
JP
Japan
Prior art keywords
chips
chip
highly integrated
integrated hybrid
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983100914U
Other languages
English (en)
Inventor
敏夫 辻
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1983100914U priority Critical patent/JPS609238U/ja
Publication of JPS609238U publication Critical patent/JPS609238U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のハイブリッドＩＣの構成図、第２図は本
考案の一実施例を示す要部構成図、第３図はＩＣチップ
が（Ｃメモリチップの場合の内部構造説明図である。 図中、１はセラミック基板、２Ｌはサイズの大きいＩＣ
チップ、２Ｓはサイズの小さいＩＣチップ、３Ｌ、３Ｓ
はホンディングワイヤ、５は絶縁層、６〜８．１０は回
路素子形成領域、９はホンディングパッドである。

Claims (2)

    【実用新案登録請求の範囲】
  1. （１）同一基板上に複数のＩＣチップを並べて搭載した
    ハイブリッドＩＣにおいて、ＩＣチップの上に該ＩＣチ
    ップの周囲のボンディングエリヤ部以上小さいＩＣチッ
    プを積み重ね、これらのＩＣチップを該基板の配線端子
    へワイヤボンディングにより接続してなることを特徴と
    する高集積ハイブリッドＩＣ０
  2. （２）積み重ねられるＩＣチップは、上、下部のものと
    も同じ大きさの回路素子形成部を持ち、そして下部のＩ
    Ｃチップは上部のＩＣチップより広い周辺部を持ち、該
    周辺部の上部ＩＣチップより外に出る部分にホンディン
    グバットが形成されてなることを特徴とする実用新案登
    録請求の範囲第（１）項記載の高集積ハイブリッドＩＣ
    ０（３）積み重ねられるＩＣチップはともにＩＣメモリ
    であり、上、下のＩＣチップの電源、データ、およびア
    ドレス各ホンディングパッドは基板の同じ配線端へワイ
    ヤボンディングされてなることを特徴とする実用新案登
    録請求の範囲第（１）項または第（２）項記載の高集積
    ハイブリッドＩＣ０
JP1983100914U 1983-06-29 1983-06-29 高集積ハイブリツドｉｃ Pending JPS609238U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983100914U JPS609238U (ja) 1983-06-29 1983-06-29 高集積ハイブリツドｉｃ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983100914U JPS609238U (ja) 1983-06-29 1983-06-29 高集積ハイブリツドｉｃ

Publications (1)

Publication Number Publication Date
JPS609238U true JPS609238U (ja) 1985-01-22

Family

ID=30238525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983100914U Pending JPS609238U (ja) 1983-06-29 1983-06-29 高集積ハイブリツドｉｃ

Country Status (1)

Country Link
JP (1) JPS609238U (ja)

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