JPS6057227B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device in which a wiring body using a polycrystalline silicon layer is formed.

As a method for reducing the resistance value of wiring using a polycrystalline silicon layer,
There is a method in which a platinum layer is deposited on a polycrystalline silicon film, followed by heat treatment to form a platinum silicide layer on the polycrystalline silicon layer to form a wiring with a low resistance value.

For example, Journal of Electrochemic
An example of this is the report described in Journal of Electrochemical Society, 197 pages, pp. 1714-171. However, in the above-mentioned literature, the formation temperature of the platinum silicide layer is 6.
It has been reported that the resistance value changes rapidly when the temperature is 500 C or higher and a high concentration of impurity is added to the polycrystalline silicon layer.

Further, the behavior of the resistance value of the platinum silicide layer after heat treatment at 650'C or less was unknown. The purpose of this invention is to provide a technology for manufacturing a wiring body having a transition metal silicide layer on polycrystalline silicon with high accuracy and reproducibility, and in which the resistance of the formed wiring body does not change significantly depending on the heat treatment temperature. It's about doing.

In this invention, first, a transition metal film such as platinum is deposited on a polycrystalline silicon layer that does not contain impurities or contains a very small amount of impurities and has a specific resistance of 1 Ωα or more, and then
A wiring body having a metal silicide layer such as a platinum silicide layer is formed on a polycrystalline silicon layer by heat treatment at a temperature of 6000 C'C to 6000 C'C.

When formed in this manner, the dependence of the resistance value of this wiring body on the heat treatment temperature is extremely small, and the resistance value itself is also small. Hereinafter, the present invention will be described in detail based on examples and with reference to the drawings.

First, as shown in FIG. 1a, a silicon dioxide layer 2 with a thickness of 0.1 to 1 μm is formed on one surface of a silicon single crystal substrate 1, and then a silicon dioxide layer 2 is formed in contact with the upper surface of the silicon dioxide layer 2. A crystalline silicon layer 3 is deposited to a thickness of 0.1 to 1 μm.

This polycrystalline silicon layer 3 is deposited using thermal decomposition of silane (SiH) at 600 to 700'C to make the polycrystalline silicon surface smooth, and the resistivity of this polycrystalline silicon layer is is approximately 1 (PΩ-cm). Note that a normal MOS type or bipolar type transistor may be provided in advance near the surface of the silicon single crystal substrate 1 before the silicon dioxide 2 is formed. Next, as shown in FIG. 1b, a platinum layer 4 is deposited to a thickness of 0.05 to 0.2 μm in contact with the upper surface of the polycrystalline silicon layer 3.

The platinum layer 4 is deposited by sputtering or electron beam evaporation. Subsequently, as shown in FIG.
, 10 to 3 in an inert gas such as nitrogen or argon.
Heat treated to a high level.

This heat treatment forms a platinum silicide layer 5 between the polycrystalline layer 3 and the platinum layer 4. After the heat treatment, the film thicknesses of the polycrystalline silicon layer 3 and the platinum layer 4 are each thinner than the values before the heat treatment. Finally, as shown in Figure 1d, about 8
Platinum layer 4 is removed by immersion in 0'C aqua regia, and the surface of platinum silicide layer 5 is exposed to produce a low resistance wiring body composed of polycrystalline silicon layer 3 and platinum silicide layer 5. A semiconductor device having the following can be obtained.

A curve 8 in FIG. 2 is a curve diagram 5 showing the relationship between the layer resistance value and the heat treatment temperature of the wiring body made of polycrystalline silicon and platinum silicide produced according to the above embodiment.

Here, the platinum film thickness was 1000A, and the heat treatment time was 1
As shown in the same figure, when the heat treatment temperature ranges from 400℃ to 600℃, the layer resistance value is about 3Ω/hole, and when the heat treatment temperature is 700℃ or higher, rapidly increasing.

Similar trends were observed for other film thicknesses and heat treatment times. That is,
It can be seen that by performing heat treatment in the range of 400° C. to 600° C. to form platinum silicide, the dependence of the layer resistance value on the heat treatment temperature is extremely small, and the layer resistance value is also small.

As described above, according to the method of manufacturing a semiconductor device of the present invention, the dependence of the layer resistance value on the heat treatment temperature can be made extremely small, so even if the heat treatment temperature fluctuates,
A semiconductor device having a wiring body with a low resistance value can be manufactured with good reproducibility and precision, and is extremely effective in practice.

Further, in characteristic 8 of FIG. 2, 400° C. is the lowest temperature at which a metal silicide is reliably formed, and if the temperature is lower than this, reproducibility becomes poor. On the other hand, if the heat treatment temperature is made higher than 800° C., the layer resistance increases rapidly and the surface becomes rough. Therefore, under the conditions specified in the present invention, a platinum silicide layer having a low resistance value and a small deviation in resistance value depending on the product can be obtained with good reproducibility.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a curve diagram showing the relationship between the layer resistance value of the wiring body and the heat treatment temperature. 1...Silicon single crystal substrate, 2...Silicon oxide layer, 3...High resistance polycrystalline silicon layer, 4...
Platinum layer, 5, 7...Platinum silicide layer, 6...
...Low resistance polycrystalline silicon layer.

Claims (1)

[Claims] 1 A substrate whose main surface is selectively covered with an insulating film does not contain impurities or contains a very small amount of impurities (10^5Ω)
A step of forming a polycrystalline silicon film with a high resistivity of cm or more, a step of forming a platinum film on the polycrystalline silicon film, and a heat treatment of the structure at 400°C to 600°C to form a platinum silicide layer. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.