JPS6218021A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lessen and stabilize the contact resistances between the substrate and the wiring layers and to obtain a semiconductor device of high-speed efficiency at a high yield by a method wherein the natural oxide film on the surface of the substrate is removed in a vacuum state and the conductive layers are formed on the substrate while a vacuum state is held. CONSTITUTION:For connection of P<+> impurity regions 6 and 7 with wiring layers 12 and 13, amorphous Si are evaporated on the surfaces of the P<+> impurity regions 6 and 7 exposed in a vacuum state, and are heated, and moreover wiring material are evaporated while a vacuum state is held. According to such a ways, the natural oxide films formed on the surfaces of the P<+> impurity regions 6 and 7 vanish to suppress new formation and then the surfaces of the P<+> impurity regions 6 and 7 and the wiring material films can be connected to each other in the state intact. By this way, the contact resistances between the P<+> impurity regions 6 and 7 and the wiring layers 12 and 13 can be suppressed to a small and stable value.

Description

[Detailed description of the invention] (Technical field of invention) The present invention relates to a method for manufacturing a semiconductor device.

[Technical beginning of the invention and its problems]

A conventional method for manufacturing a MOS t-transistor will be explained with reference to FIG. For example, by forming a field oxide film 2 on the surface of an n-type silicon semiconductor substrate 1 with a plane orientation (100) and forming an n-type inversion prevention layer 3 on the surface of the semiconductor substrate 1 under this field oxide film 2, The element regions are separated (FIG. 3(a)).

The surface of the semiconductor substrate 1 in this element region has a thickness of 100 to 5
00 gate oxide film 4 is formed.

A gate electrode 5 made of polycrystalline silicon doped with an n-type impurity is formed at a predetermined location on this gate oxide film 4. Using the gate electrode 5 and field oxide film 2 as a mask, n-type impurities such as boron are ion-implanted.
P+ impurity regions d and 7 as source and drain regions are formed on the surface of the semiconductor substrate 1 in the element region (FIG. 3(b)).

Next, apply CVD (Chemical Vapo) to the entire surface.
r 0eposition) Oxidation 11! After depositing i19, contact balls 10 and 11 are opened at positions corresponding to P+ impurity regions 6.7, respectively. Furthermore, after aluminum (Δ1) is vapor-deposited over the entire surface, wiring layers 12 and 13 are formed by patterning. In this way, the P+ impurity regions 6.7 as the source region and the drain region are connected to the wiring layer 12.7 through the contact holes 10.11, respectively.
13 (Fig. 3(C)).

However, in the above manufacturing method, the contact hole 10.11 is exposed to an atmosphere containing a gas such as oxygen that reacts with silicon to form an insulating compound between the opening of the contact hole 10.11 and the vapor deposition of aluminum.
A natural oxide film is formed on the surfaces of the P+ impurity regions 6 and 7 exposed by the first hole.

For this reason, the contact resistance between the P+ impurity regions 6, 7 and the wiring layer 12°13 becomes a large and highly variable value,
There has been a problem in that this hinders the formation of circuits having desired characteristics, leading to a decrease in the manufacturing yield of highly integrated circuits.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and is a method for manufacturing a semiconductor device, which suppresses the contact resistance between the semiconductor substrate and the wiring layer to a small and stable value, and manufactures a high-speed performance semiconductor device at a high yield. The purpose is to provide

[Summary of the invention]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a first step of removing a natural oxide film formed on the surface of a semiconductor substrate in a vacuum state, and a step of removing a natural oxide film formed on the surface of a semiconductor substrate for 24 hours while maintaining the vacuum state. and a second step of forming an electric layer. In this first step, amorphous silicon is deposited on the semiconductor substrate to a thickness of 10 to 100 ℃ in a vacuum apparatus at 600 to 900℃.
It is desirable to remove the native oxide film by heating at .degree. C. or by ion sputtering.

As a result, the natural oxide film on the surface of the semiconductor substrate is removed, new formation of the natural oxide film is suppressed, and ohmic connection between the semiconductor substrate and the conductive layer can be obtained in that state.

[Embodiments of the invention]

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. For example, a field oxide film 2 is formed on the surface of an n-type silicon semiconductor substrate 1 with a (100) plane orientation, and an n-type inversion prevention layer 3 is formed on the surface of the semiconductor substrate 1 below this field oxide film 2. This separates the element regions (FIG. 1(a)).

Subsequently, a thermal oxidation process is performed to oxidize the gate to a thickness of 1008 to 500 mm on the surface of the semiconductor substrate 1 in the element region. Form J4. Polycrystalline silicon doped with n-type impurities is deposited on gate oxide film 4, and gate electrode 5 is formed at a predetermined location by patterning. Using the gate electrode 5 and field oxide film 2 as a mask, n-type impurity such as boron is ion-implanted, activated by annealing, and P) impurity regions 6 as source and drain regions are formed on the surface of the semiconductor substrate 1 in the element region. .7 are formed separately from each other (Fig. 1(b)).

Next, after depositing a CVDM film 8 on the entire surface, RIE
The CVD oxide film 8 is etched by a reactive ion etching method. As a result, the CVD oxide film 8 remains on the side surfaces of the field oxide film 2 and the gate electrode 5, and the upper surface of the gate electrode 5 and the P+
Most of the surface of the impurity region 6.7 is exposed (see FIG.
C)).

Next, contact holes 10.degree. 11 are formed at positions corresponding to the P+ impurity regions 6.7 on which the CVD oxide film 9 as an interlayer insulating film is deposited over the entire surface. Then, the semiconductor substrate 1 is transferred into a vacuum chamber d and placed in a vacuum state. First, amorphous silicon is deposited to a thickness of about 10 layers, and then heated to a temperature of about 850 degrees Celsius or higher. As a result, a chemical reaction 3iQ +3i occurs between the natural oxide film formed on the surface of the P+ impurity dull substance 1j/16.7 exposed by the opening and the amorphous silicon deposited thereon.
-→2SiO↑ is promoted and the natural oxide film disappears and is covered. Subsequently, in a vacuum state, the wiring material A! ! Deposit.

The semiconductor substrate 1 is taken out from the vacuum apparatus and subjected to vapor deposition.
Wiring layers 12 and 13 are formed by patterning Q (FIG. 1(d)).

According to this embodiment, when connecting the P+ impurity region 6.7 and the wiring layer 12.13, amorphous silicon is deposited on the exposed surface of the P+ impurity region 6.7 in a vacuum state and heated. , by further depositing the wiring material while maintaining the vacuum state, the P+ impurity region 6.7
The natural oxide film formed on the surface disappears, its new formation is roughly suppressed, and the P+ impurity head 1 is left as it is.
467 surface and wiring material can be connected.

As a result, P+ impurity head 1g67 and wiring layer 1
2. The contact resistance with 13 is small and stable (can be suppressed directly).

In the above embodiment, amorphous silicon vapor deposition and heating to decompose the oxide film were used to eliminate the natural oxide film on the surface of the P+ impurity region 6°7, but methods such as ion sputtering may also be used. It is possible.

In addition, in the above example, aluminum was used as the wiring material (
A1) was used, but platinum (Pt) and molybdenum (M
o) Pure metals such as tungsten (W) or tantalum (Ta) or silicides thereof may be used.

Generally speaking, the above embodiments have described MOS transistors, but the present invention is applicable to all methods of manufacturing semiconductor devices that require good ohmic connection between a semiconductor substrate and a conductor formed on the semiconductor substrate. can do.

FIG. 2 shows a graph comparing the contact resistance characteristics of the semiconductor device according to the present invention with the conventional one.

This is a result of forming 100 contact hole chains on four types of wafers with different contact hole niceness, and measuring the contact resistance. Contact resistance due to conventional manufacturing methods increases rapidly as the contact hole size decreases, and
The variation range of contact resistance also increases as the contact hole size becomes smaller; for example, when the contact hole size is about 1.4 μm or less, the variation range of contact resistance becomes 100Ω or more. In contrast, the contact resistance according to the manufacturing method of the present invention has a small value for each contact hole size, and the rate of increase as the contact hole size decreases is not so large. Further, the fluctuation range of contact resistance is also significantly small, for example, 500 or less for a contact hole size of 1.0 μm. As described above, according to the present invention, a sufficiently small and stable contact resistance can be obtained even if the contact hole is small.

[Effects of 1 x 1] As described above, according to the present invention, the contact resistance between the semiconductor 1 root and the wiring layer can be suppressed to a small and stable value, and as a result, high-speed performance semiconductor devices can be manufactured with high yield. can be manufactured.

[Brief explanation of the drawing]

FIG. 1 is a dimensional drawing showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a graph showing contact 1 to resistance of the semiconductor device according to the present invention, and FIG. 3 is a graph showing a conventional semiconductor device. This is a process diagram of the manufacturing method. 1... Semiconductor substrate, 2... Field oxide film, 3...
...N-type inversion prevention layer, 4...gate oxide film, 5...
Gate electrode, 6, 7...P+ impurity region, 8, 9...
・CVD oxide film, 10.11... Contact ball, 12°13... Wiring layer. Applicant's agent: Sato Q 1.0 2.0
3. Q Konitawa Tohono L size (/
, Lmel) Figure 2 (C) Helmet figure 3

Claims (1)

[Claims] 1. A first step of removing a natural oxide film formed on the surface of a semiconductor substrate in a vacuum state, and a second step of forming a conductive layer on the semiconductor substrate while maintaining a vacuum state. A method for manufacturing a semiconductor device, comprising: 2. The manufacturing method according to claim 1, wherein the first step is a step of depositing amorphous silicon on the semiconductor substrate in a vacuum apparatus and heating it. Production method. 3. In the manufacturing method according to claim 2, the thickness of the amorphous silicon deposited on the semiconductor substrate is 10 Å to 100 Å, and the heating temperature after deposition is 600° C. to 900° C. A method for manufacturing a semiconductor device, characterized in that: 4. The manufacturing method of a semiconductor device according to claim 1, wherein the first step is a step of performing ion sputtering on the semiconductor substrate in a vacuum apparatus.