JPH06318563A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having an electrode interconnection structure of low contact resistance and a high thermal stability on a shallow diffusion layer. CONSTITUTION:An impurity diffusion layer 4 is formed on a semiconductor substrate 1 which has a (001) plane as a principal plane. On the whole surface of the impurity diffusion layer or on a part of an insulating film which is exposed in an opening, an orthorhombic-system single-crystalline high-melting point metal compound film 15 is formed by selective vapor phase growth. By this method, a contact resistance in a silicide/Si interface can be reduced and a high reliable junction can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a metal compound film on a shallow impurity layer.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit on one chip have been formed in important parts of computers and communication devices. It is used a lot. This L
Improving the performance of the SI alone is important for improving the performance of the entire device. Since this can be achieved by, for example, increasing the integration degree of the LSI, it is necessary to miniaturize the basic element of the LSI, for example, a field effect transistor (FET). Therefore, it is required to make the source / drain regions shallower as the gate of the FET is shortened. For example, a low acceleration ion implantation method is widely used for forming these regions. By using this method, a shallow source / drain region of 0.1 μm or less can be formed, and it is possible to form a FET that is further miniaturized and has high performance. However,
Thus, the impurity layer formed only by the ion implantation method has a high resistance and a sheet resistance of 100Ω / □ or more. F
In order to increase the ET speed, it is necessary to reduce the sheet resistance of this impurity layer and improve the drain current flow.
Furthermore, as the diameter of the contact hole becomes smaller, Si in the Al.Si.Cu alloy used for the electrode wiring material precipitates in the hole and increases the contact resistance. It is necessary to form a barrier metal between the Si and Cu alloys. In order to solve the above-mentioned problems, a method of metallizing a part of the impurity layer or the inside of the contact hole opening has been considered, for example, a method called salicide. This is shown in FIG.

In this method, first, an 800 nm field oxide film 2 is formed on an n-type Si substrate 1 by an embedding method. 10 nm in the element formation region surrounded by the oxide film 2
After the gate oxide film 3 ₁ and the doped polycrystalline layer 3 ₂ having a thickness of 150 nm are sequentially formed as a gate electrode, this is processed into a gate shape by etching to form a laminated film. After depositing the insulating film ₃₅ after this to a thickness of 150nm, thereby forming the insulating film ₃₅ of approximately 150nm on the sidewall of the gate electrode is processed by anisotropic etching. Next, the impurity diffusion layer 4 is formed on the substrate 1.
Is formed using a well-known ion implantation method, and then titanium (T
i) depositing film 13 to a thickness of 40 nm (FIG. 6)
(A)). This is heated by lamp annealing to form a titanium silicide (TiSi ₂ ) film 15 on the impurity diffusion layer 4 (FIG. 6B). After that, unreacted Ti is removed by etching, and finally the insulating film 10 is provided to form an opening, and then the wiring 17 is formed.
Are formed (FIG. 6C).

Using this method, for example, a silicide having a thickness of 80 nm can be formed, and the sheet resistance can be reduced to 2-3 Ω / □. However, recent energetic studies have revealed that the following problems occur in this type of method.

When the TiSi ₂ film is formed by the above method T
In order to reduce the sheet resistance of iSi ₂ , it is necessary to perform high temperature heat treatment at 850 ° C. or higher. As a result, the dopant concentration at the interface between the TiSi ₂ film and the impurity diffusion layer decreases, and the contact resistance increases. Furthermore, since the TiSi ₂ film formed by such a solid phase reaction is a polycrystalline film,
The interface between the i ₂ film and the Si substrate has irregularities for each TiSi ₂ crystal grain. Since the depth of this unevenness reaches as much as 50% of the average film thickness of TiSi ₂ , when applied to a semiconductor device having a shallow diffusion layer with a junction depth of 0.1 μm or less, the electric field concentration effect induced by the interface unevenness Increases junction leakage. Further, when a high temperature heat treatment of 850 ° C. or higher is applied, a so-called agglomeration phenomenon occurs, in which TiSi ₂ crystal grains are aggregated, so that the sheet resistance of the film is increased and the junction breakdown is caused to secure the reliability of the element. Things became difficult.

Further, since the contact surface between the TiSi ₂ film and the Si substrate is different for each crystal grain of TiSi ₂ , the contact resistance varies depending on the plane orientation, and particularly a stable contact resistance can be obtained with a fine contact of 0.5 μm or less. Was difficult.

In addition, N is used as a material replacing TiSi _2.
A salicide technique using an iSi ₂ film has also been proposed, but in this case as well, there was a problem that the interface shape was changed by heat treatment at 850 ° C. or higher.

[0008]

In the conventional semiconductor device, when a shallow impurity layer of 0.1 μm or less is formed, since the metal compound layer is a polycrystalline film, unevenness is generated at the interface with the semiconductor substrate and the heat resistance is high. Deteriorates the junction characteristics of the shallow impurity diffusion layer. Further, there is a problem that the contact resistance with Si is not stable. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a low resistance contact and a manufacturing method thereof.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and a semiconductor substrate having a (001) plane as a main surface and an impurity diffusion layer selectively formed on this substrate. And a semiconductor device having an orthorhombic epitaxial refractory metal compound film formed on the impurity diffusion layer.

Further, in the present invention, in the refractory metal compound film, the crystal main axis direction is <001> of the semiconductor substrate.
Provided is a semiconductor device having a film substantially aligned with the axis. Furthermore, according to the present invention, a step of forming an impurity diffusion layer on a semiconductor substrate having a (001) plane as a main surface and a gas containing a refractory metal halogen compound are set to a temperature higher than the temperature of the semiconductor substrate. And a step of supplying the semiconductor substrate to the semiconductor substrate through a region, and manufacturing a semiconductor device in which a rhombic single crystal refractory metal compound film is formed on the impurity diffusion layer by a vapor growth method in a reduced pressure atmosphere. Provide a way.

[0011]

According to the present invention, in the vapor phase growth method under a reduced pressure atmosphere, the growth of the refractory metal compound film proceeds by isotropic growth of nuclei of the refractory metal compound generated on the surface of the semiconductor substrate. During the growth process of the nuclei of the refractory metal compound, it is possible to grow while maintaining the energetically most stable orientation relationship with the semiconductor substrate. Therefore, it is possible to form a flat interface between the flat refractory metal compound film and the semiconductor substrate, and it is possible to provide a semiconductor element having a contact resistance that is sufficiently low and has little variation without causing a junction leak defect. Further, by reducing the pressure, the growth rate of the refractory metal compound film can be controlled, and it is possible to prevent the unreacted gas, which causes the increase in the specific resistance, from entering the film.

Further, according to the present invention, for example, it is made of a conductor containing a semiconductor element of the same kind as the semiconductor substrate or a refractory metal element of the same kind as the refractory metal compound film, and is set to a temperature higher than the temperature of the semiconductor substrate. The epitaxial growth reaction can be promoted by introducing a reaction gas into the generated heating element region. The reason for this is that the metastable refractory metal halogen compound is easily adsorbed on the surface of the semiconductor substrate, and the dissociation thereof progresses sufficiently fast, so that an impurity element such as halogen is hard to be taken into the film and a defect is hard to occur. It is considered that this is because the epitaxial growth is promoted. Therefore, the refractory metal compound film can be grown with high reliability even at low temperatures.

[0013]

EXAMPLES Details of the present invention will be described with reference to examples. FIG. 1 is a sectional view showing a field effect transistor according to an embodiment of the present invention in the order of manufacturing steps.

First, n-type Si whose main surface is (001)
A field oxide film 2 of 800 nm is formed on the substrate 1 by an embedding method. In the element formation region surrounded by the oxide film 2, a gate oxide film 3 _{1 having} a thickness of 10 nm, a polycrystalline layer 3 ₂ having a thickness of 50 nm, and a tungsten silicide (WS) having a thickness of 150 nm are formed.
i ₂₎ layer 3 ₃ and this was sequentially deposited CVD-SiO ₂ film 3 ₄ processed by etching the gate shape providing a laminated film. The After CVD-SiO ₂ film was processed by anisotropic etching after deposition to a thickness of 150nm to form the SiN film ₃₅ on the sidewall of the gate. Next, a 10 nm SiO ₂ film 6 is formed on the exposed Si surface, and BF ₂ ⁺ ions are added to
Inject 5 × 10 ¹⁵ cm ⁻² with keV and perform 10 in N ₂ atmosphere.
Approximately 0.1 μm by applying heat treatment at 00 ° C for 20 seconds
The shallow p ⁺ diffusion layer 4 was formed (FIG. 1A).

After that, the substrate is introduced into a vacuum device and BCl
₃ By performing plasma treatment, the thin SiO ₂ film 6 on the p ⁺ diffusion layer 4 is removed. Next, once in the vacuum device 5 × 1
After reducing the pressure to 0 ^-7 Torr or less, the Si substrate 1 is heated to 70
Heat to 0 ° C. Next, 0.5 sccm of TiCl ₄ gas is introduced into the vacuum device. At this time, TiCl ₄ gas is S
Prior to reaching i, it passes through the Si heating element region heated to 900 ° C. and then reaches the film forming region. At this time, the pressure of TiCl ₄ gas was 1 × 10 ⁻⁴ Torr. As a result, about 50 nm of TiS is formed on the p ⁺ diffusion layer 4.
The i ₂ film layer 15 could be formed (FIG. 1B).
At this time, TiSi ₂ was not formed on the insulating film.

As a result of evaluating the film quality of this TiSi ₂ film,
It was confirmed that the crystal structure was an orthorhombic C54 phase,
At the same time, the Si (001) plane and the (001) plane of TiSi ₂ were parallel. FIG. 2 shows the X-ray diffraction spectrum of the TiSi ₂ film, but only a sharp (004) peak appears, which shows that the crystallinity of TiSi ₂ is very good over the entire surface. Here, the crystal axis of TiSi ₂ is a,
If the lengths of the axes b and c are da, db, and dc, respectively,
It is arranged so that dc>da> db. Furthermore this T
A detailed evaluation of the orientation relationship of the iSi ₂ film revealed that TiSi ₂
It was confirmed that the <100> axis of the film coincided with the [110] direction of Si. At this time, the sheet resistance of the TiSi ₂ film was about 5Ω / □. The misorientation was within 6 ° in all cases.

Next, a laminated film of a CVD-SiO ₂ film 10 ₁ and a BPSG film 10 ₂ is deposited on the entire surface as an interlayer insulating film to a thickness of 1.0 μm, and then 85 in a POCl ₃ atmosphere under atmospheric pressure.
Gettering annealing was performed at 0 ° C. for 60 minutes. Thereafter the source, the contact hole provided on the drain region, wherein, for example, selective CVD-W film 11, Ti film 11 _3, Ti
The field effect transistor is completed by forming the electrode wiring of the laminated film of the N film 11 ₁ and the Al · Si alloy 11 ₂ (FIG. 1).
(C)).

As described above, according to the method of the above embodiment, Si
The mechanism capable of forming a good epitaxial thin film of TiSi ₂ film on (001) can be explained as follows. In the conventional TiSi ₂ formation method, Ti is formed on a Si substrate.
After the thin film is deposited, high temperature heat treatment is performed to advance the reaction. In this case, the reaction is dominated by the diffusion process of Si atoms into the Ti film, and the formation of silicide progresses uniformly in the plane. Since the TiSi ₂ film is formed in the intermediate portion between the Ti film and the Si substrate, stress is always applied from the surroundings during the growth process. As a result, it becomes impossible to cause epitaxial growth.

On the other hand, in the method of this embodiment, since the vapor phase growth method under reduced pressure is used, the growth of the TiSi ₂ film proceeds by isotropic growth of TiSi ₂ nuclei generated on the surface of the Si substrate. . TiSi The _binuclear growth procedure not stress is applied, TiSi ₂ nuclei becomes possible to grow while maintaining the energetically most stable orientation relationship with the substrate Si. Furthermore, in the above-mentioned embodiment, the surface of the Si substrate is cleaned immediately before forming TiSi ₂ , which makes it possible to suppress the orientation fluctuation of TiSi ₂ nuclei and at the same time sufficiently increase the nucleation density. ing.

In the above embodiment, the pressure of TiCl ₄ was set to 1 × 1.
Although shown at 0 ^-4 Torr, various experiments have shown that the pressure of TiCl ₄ is 1 × 10 ^-3 Tor.
It was confirmed that good epitaxial growth of the TiSi ₂ film was possible within the range of rr or less. 1 x 10 ^-3 Torr
When the above pressure is used, the film formation rate of the TiSi ₂ film becomes too high, so that the epitaxial relationship is disturbed, and at the same time unreacted TiCl ₄ gas in the gas phase is taken into the film, Caused an increase in resistivity. Further, when the condition of 1 × 10 ⁻⁵ Torr or less was used, a sufficient film formation rate could not be obtained.

Further, when the TiCl ₄ gas is introduced into the substrate, a portion of TiCl ₄ once reacts with the heating element Si by passing through the Si heating element region heated to a high temperature, and T
iCl _x (1 ≦ X ≦ 3) is formed. As a result, TiCl ₄ and TiCl _x (1 ≦ X ≦ 3) are simultaneously supplied onto the Si substrate. Since TiCl _x has a stronger oxidizing power for Si than TiCl ₄ , it easily reacts with the Si substrate even at a low temperature to form a TiSi ₂ film.

That is, here, TiCl 3 is formed on the surface of the Si substrate.
_X is easily adsorbed and the reaction proceeds sufficiently fast. Therefore, elements such as Cl ₂ are less likely to be incorporated into the film, and defects are less likely to occur, so that it is considered that the epitaxial growth of the TiSi ₂ film is promoted.

Furthermore, TiSi which is cleaner than that on the Si substrate
_{On the 2} film, TiCl ₄ is easily decomposed, so that T
The growth of the iSi ₂ film is promoted. As described above, a metastable high-melting-point metal halogen compound, in particular, a compound containing a smaller number of halogens than the number of halogens in the stable-state high-melting-point metal halogen compound may be generated. A membrane can be obtained.

Further, in the method of the above embodiment, since the natural oxide film (SiO _x ) on the Si surface is removed by TiCl _x ,
A uniform film can be formed without special pretreatment such as cleaning just before the TiSi ₂ film is formed.

Furthermore, in the above embodiment, the deposition temperature is 70.
Although the case of 0 ° C. was described, the epitaxial growth of the TiSi ₂ film was confirmed at a temperature of 680 ° C. or higher. However, when a temperature higher than 800 ° C. is used, it is recognized that the epitaxial relationship is disturbed as the film formation rate increases, and at the same time chlorine generated in the reaction process etches the substrate Si and causes a bonding failure. . The temperature range in which a particularly good epitaxial film is obtained using the method of the above example is 700 to 800 ° C., and the typical film forming rate at this time is 5 to 100 nm / min.

As a result of evaluating the junction leakage characteristics of the p ⁺ diffusion layer of the field effect transistor formed by the above method, it was confirmed that the junction leakage characteristics were as good as those of the reference on which the TiSi ₂ film was not formed. FIG. 3 shows the case where the epitaxial TiSi ₂ thin film is formed in the above-mentioned embodiment,
The junction leakage characteristics in the case of forming a polycrystalline TiSi ₂ thin film by the conventional method are shown in comparison. It is shown that the conventional polycrystalline thin film causes agglomeration due to a thermal process at 850 ° C. and causes junction breakdown. I understand. The reason why the epitaxial TiSi ₂ thin film thus formed according to the present invention has high heat resistance can be explained as follows.

In the conventional polycrystalline TiSi ₂ film, since each crystal grain has different orientations, crystal grain boundaries having various orientation relationships exist, and the system is in a metastable state with high energy. When high temperature heat treatment is performed, a driving force that minimizes the surface area of crystal grains is generated in order to reduce the energy of the system. This results in T
At the same time as the iSi ₂ film aggregates and the uniformity of the film is impaired,
Bond failure occurs due to large aggregated particles. On the other hand, in the epitaxial TiSi ₂ film formed by the present invention, particularly in the single crystal film, the most stable structure in terms of energy is realized from the early stage of growth as described above. Therefore, the rearrangement of the structure for lowering the energy is required. No need to do. Further, since there is no crystal grain boundary with high energy due to the variety of orientations, the driving force for eliminating the grain boundary does not occur. This results in TiSi ₂
It is considered that the heat resistance of the film is improved. It is confirmed that the 10-nm TiSi ₂ thin film formed in this example is also a uniform C54 phase epitaxial film when evaluated in detail. Recently, when TiSi ₂ is formed by the conventional technique, the crystal structure is C49 in a thin film of 20 nm or less.
It is stable due to the high resistance structure represented by the phase, 900 ° C
It has been reported that the transition to the C54 phase having low resistance does not proceed even if the high temperature heat treatment is applied. On the other hand, when the method of the present embodiment is used, it is also a great feature that the C54 phase having a low resistance can be formed at a low temperature of about 700 ° C. regardless of the film thickness.

In the above embodiment, the deposition temperature is 700 ° C.
As described above, the epitaxial growth of the TiSi ₂ film was confirmed at a temperature of 680 ° C. or higher. However, 8
When a temperature higher than 00 ° C. was used, it was observed that the epitaxial relationship was disturbed as the film formation rate increased, and at the same time chlorine generated in the reaction process etches the substrate Si and causes a bonding failure. The temperature range in which a particularly good epitaxial film is obtained using the method of the above example is 700 to 800 ° C., and the typical film forming rate at this time is 5 to 100 nm / min.

Although the temperature of the Si heating element is set to 900 ° C., it may be set to a temperature higher than the temperature of the semiconductor substrate which is the film forming region. Particularly, it is preferably 750 ° C. or higher and 1000 ° C. or lower, and a sufficient effect could be obtained in this temperature range. Further, the pressure of TiCl ₄ is not limited to the above value, and good results can be obtained in the range of 5 × 10 ⁻⁵ Torr or more. Typical film formation rate is 5-100 nm / min
And the best epitaxial growth film was obtained in the case of 5 to 50 nm / min.

In addition to the Si heating element, TiSi ₂
As a result of investigating the heating element as well, TiSi
_It was possible to form _two films. The reason is that TiCl ₄ to TiCl _X (1
≦ X ≦ 3) is formed. It is considered that the process of forming TiCl _x is dominated by the process in which TiCl ₄ adsorbed on the surface of TiSi _{2 at} high temperature is dissociated into TiCl _x by a catalytic action when a TiSi ₂ heating element is used.

Next, another embodiment of the present invention will be described with reference to FIG. First, an 800 nm field oxide film 2 is formed by thermal oxidation on an n-type Si substrate 1 whose main surface is (001). BF is formed in the element formation region surrounded by the oxide film 2.
₂ ⁺ ions are implanted at 35 eV at 5 × 10 ¹⁵ cm ^-2 and N _{2 is} injected.
A shallow p ⁺ diffusion layer 4 of about 0.1 μm is formed by applying heat treatment at 1000 ° C. for 20 seconds in the atmosphere. Next, after depositing a laminated film of a CVD-SiO ₂ film 10 ₁ and a BPSG film 10 ₂ as an interlayer insulating film to a thickness of 1.0 μm,
A contact hole is provided on the diffusion layer (FIG. 4A).
After washing this substrate with a dilute aqueous solution of hydrofluoric acid, it is introduced into a vacuum apparatus and heated to 600 ° C. At this time, the pressure in the chamber was constantly maintained at 1 × 10 ⁻⁶ Torr or less. After that, TiCl ₃ (CH ₃ ) gas was introduced into the chamber. At this time, the TiCl ₃ (CH ₃ ) gas reaches the film formation region after passing through the Si heating element region heated to 800 ° C. before reaching the Si substrate. At this time, TiCl ₃ (C
The pressure of H ₃ ) gas was set to 1 × 10 ⁻⁴ Torr. As a result, the TiSi ₂ film 15 having a thickness of about 15 nm was selectively formed only on the exposed portion of the diffusion layer in the contact hole (FIG. 4B). After this, TiSi in the contact hole
_The CVD-W film 11 is continuously grown only on the surface ₂ by the selective vapor phase epitaxy method, and the Ti film 11 ₃ , TiN film 11 ₁ , Al
The upper electrode wiring is completed with a laminated film of Si / Cu11 ₂ films (FIG. 4C).

TiS formed using the second embodiment
When the characteristics of the i ₂ film were evaluated in the same manner as in the first embodiment, the crystal structure was Si (001) // TiSi ₂ (00
It was confirmed that the film was a good epitaxial film of C54-TiSi ₂ represented by 1).

Further, when the electrical characteristics of the contact formed with the TiSi ₂ film of the above-described embodiment were evaluated, it was confirmed that the contact showed a thermally stable low resistance characteristic as in the first embodiment.

In the above first and second embodiments, the process of forming TiSi ₂ using TiCl ₄ and Si has been described. On the other hand, in the third embodiment, TiCl ₄ and SiH ₄
The case where the mixed gas of is used will be described with reference to FIG.

Similar to the second embodiment, the field oxide film 2, the shallow p ⁺ diffusion layer 4, the CVD-SiO ₂ film 10 ₁ and the BPSG film are formed on the n-type Si substrate 1 whose main surface is (001). After forming the 10 ₂ laminated film, a contact hole is provided on the diffusion layer (FIG. 5A). After washing this substrate with a dilute aqueous solution of hydrofluoric acid, it is introduced into a vacuum apparatus and heated to 650 ° C. At this time, the pressure in the chamber is always 1 × 10 ^-6 Tor
It was kept below r. After this, TiCl ₄ gas and SiH ₄ gas were introduced into the chamber. At this time, TiCl ₄ gas and SiH ₄ gas are introduced into the chamber through separate ports, and TiCl ₄ passes through the Si heating element region heated to 900 ° C. or more before reaching the substrate and then reaches the film forming region. I have to. At this time, TiCl ₄ gas and SiH ₄
Gas pressure is 3 × 10 ^-4 Torr and 1 × 10 ^-3 Tor, respectively
rr. As a result, the epitaxial T of about 0.7 μm is formed only in the exposed portion of the diffusion layer in the contact hole.
The iSi ₂ film 15 was selectively embedded (see FIG. 5).
(B)). At this time, the penetration depth of the TiSi ₂ film 15 into the Si substrate was about 15 nm. After this, Ti film 11 ₃ , T
iN film 11 ₁ , Al. Si. A laminated film of Cu11 ₂ films is formed to complete the upper electrode wiring (FIG. 5C).

The TiSi ₂ film forming mechanism in the third embodiment can be explained as follows. Similar to the case of the second embodiment, TiCl _x is formed by passing only TiCl ₄ gas through the Si heating element region, and the substrate Si and TiCl _x react with each other in the initial stage of the reaction to form thin TiSi _2. . Next, this SiH ₄ and TiCl _x
The TiSi ₂ film is deposited by being activated by being adsorbed on the ₂ film and reacting with each other. As described above, in the third embodiment, the mechanism of the initial TiSi ₂ film forming process and the subsequent film forming process are different. This is because the Si surface has a stronger reducing power of TiCl _x and TiCl ₄ than SiH ₄ , and therefore the first TiSi ₂ formation process proceeds by reaction with Si even when SiH ₄ is added. When TiSi ₂ is formed on the substrate (first step), the reduction reaction by SiH ₄ causes T
It can be explained that iSi ₂ is deposited (second process).
Further, since the first and second processes are continuously performed, T
Even if the iSi ₂ film is thick, the epitaxial relationship is kept good. By using this example, it was possible to reduce the temperature at which TiSi ₂ is formed by the SiH ₄ reduction reaction. In the above example, the film formation was performed at 650 ° C., but a good buried contact could be formed at 600 ° C. or higher.

Needless to say, the present invention can be implemented by variously modifying it. For example, CVD using SiH ₄ in the source / drain regions or contact openings
Selectively uses polycrystalline Si or epitaxial S
The present invention may be applied after forming i. Although SiH ₄ is added as the reaction gas in the third embodiment, the same effect can be obtained by using SiCl ₄ , SiH ₂ Cl ₂ , Si ₂ H ₄ gas or the like. The same applies to the case where H ₂ gas is added to these gases. Furthermore, TiCl ₄ gas changes to TiCl ₃ of (CH ₃₎ gas _{or, TiCl X (1 ≦ X ≦} 2) caused by sublimating the _{TiCl 3, TiI X (1 ≦} X ≦ caused by sublimating TiI ₄ Needless to say, the same effect can be obtained when another Ti source such as 3) is used.

Further, although the above embodiment has been described on the p ⁺ -Si substrate, it goes without saying that the same technique can be applied to the n ⁺ -Si substrate. Others The present invention is not limited to the above-described embodiment, but can be variously modified and used.

[0039]

According to the present invention, since a good orthorhombic single crystal refractory metal compound film can be formed on a substrate, it has a low resistance value with little variation and a junction leak. A highly reliable epitaxial refractory metal compound contact can be formed.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention.

FIG. 2 is an X-ray diffraction spectrum showing an example of the present invention.

FIG. 3 is a diagram showing junction leak characteristics showing an embodiment of the present invention.

FIG. 4 is a process sectional view showing an embodiment of the present invention.

FIG. 5 is a process sectional view showing an embodiment of the present invention.

FIG. 6 is a process sectional view showing a conventional method.

[Explanation of symbols]

1 ... Si substrate 2 ... Field oxide film 3 ... Gate region 4 ... p ⁺ diffusion layer 6 ... SiO ₂ film 10 ... Interlayer insulating film layer 11 ... Electrode wiring layer 13 ... Ti film 15 ・ ・ TiSi ₂ film 17 ・ ・ Wiring

Claims (9)

[Claims] 1. A semiconductor substrate having a (001) plane as a main surface, and an impurity diffusion layer selectively formed on the substrate,
A semiconductor device having an orthorhombic epitaxial refractory metal compound film formed on the impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein the refractory metal compound film is a film whose crystal major axis direction substantially coincides with the <001> axis of the semiconductor substrate. 3. The refractory metal compound film has a crystallographic axis of <0 of the semiconductor substrate in any one of the directions of the principal axes.
The semiconductor device according to claim 2, wherein the film is substantially aligned with the 11> axis. 4. A step of forming an impurity diffusion layer on a semiconductor substrate having a (001) plane as a main surface, and a gas containing a metastable refractory metal halogen compound is supplied onto the semiconductor to obtain the impurities. A method for manufacturing a semiconductor device, comprising forming an orthorhombic epitaxial refractory metal compound film on a diffusion layer. 5. A step of forming an impurity diffusion layer on a semiconductor substrate having a (001) plane as a main surface, and a region containing a gas containing a refractory metal halogen compound at a temperature higher than the temperature of the semiconductor substrate. And a step of supplying it to the semiconductor substrate, wherein an orthorhombic epitaxial refractory metal compound film is formed on the impurity diffusion layer by a vapor phase growth method in a reduced pressure atmosphere. Device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the atmosphere in which the epitaxial refractory metal compound film is formed is a reduced pressure atmosphere. 7. The reduced pressure atmosphere is 1 × 10 ⁻³ Torr.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the range is from 1 × 10 ⁻⁵ Torr. 8. The region set to a temperature higher than the temperature of the substrate is a region made of a conductor containing a semiconductor element of the same kind as the semiconductor substrate or a refractory metal element of the same kind as the refractory metal compound film. 6. The method of manufacturing a semiconductor device according to claim 5, wherein. 9. The gas having a reducing power smaller than that of the semiconductor substrate is supplied to the semiconductor substrate.
Alternatively, the method for manufacturing the semiconductor device according to the above item 5.