JPS6057646A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6057646A JPS6057646A JP16541583A JP16541583A JPS6057646A JP S6057646 A JPS6057646 A JP S6057646A JP 16541583 A JP16541583 A JP 16541583A JP 16541583 A JP16541583 A JP 16541583A JP S6057646 A JPS6057646 A JP S6057646A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- silicide
- contact
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の多層配線構造に関する。[Detailed description of the invention] The present invention relates to a multilayer wiring structure of a semiconductor device.
従来、半導体装置における多層配線構造は、最も一般的
には第1図に示す如き構造をとっていた。Conventionally, a multilayer wiring structure in a semiconductor device has most commonly had a structure as shown in FIG.
すなわち、si基板1上に形成された酸化膜2士にsi
配線3が形成され、層間絶tす膜4を介して、該層間絶
縁膜4を通して開けられたコンオクト穴5を通して、A
t配線6が形成されて成るのが通例であ−た。That is, Si is applied to two oxide films formed on Si substrate 1.
The wiring 3 is formed, and the A
Usually, a t-wiring 6 was formed.
[、かじ、上記従来技術によると、多層配線のコンタク
ト部での妾触抵抗が犬となる欠点があった。[, Kaji, According to the above-mentioned conventional technology, there was a drawback that the contact resistance at the contact portion of the multilayer wiring was high.
本発明は、かかる従来技術の欠点をなくし、51種金属
等の多層配線においても接触抵抗の小さな多層配線構造
を提供することを目的とする。It is an object of the present invention to eliminate such drawbacks of the prior art and to provide a multilayer wiring structure with low contact resistance even in multilayer wiring made of type 51 metals.
上記目的を辺成するための本発明の基本的な描成は、半
導体装置に於て、Si配線表面にはモリブデン・シリサ
イド、タングステン・シリサイド、タンタルOシリサイ
ドあるいはチタン、シリサイド等のシリサイド膜が形成
され、層間絶縁膜に開けられたコンタクト穴を通して層
間絶縁膜上にAt配線を形成する場合に、コンタクト部
汲びd配線下にはモリブデン・シリサイド、タングステ
ン・シリサイド、タンタル・シリサイドあるいけチタン
譬シリ…−イド等のシリサイド膜か、あるいけモリソデ
ン、タングステン、タンタルあるいはチタン等の金属膜
が形成されて成ることを特徴とする、以下、実施例によ
り本発明を詳述中る。The basic concept of the present invention for achieving the above object is that a silicide film such as molybdenum silicide, tungsten silicide, tantalum O silicide, titanium silicide, etc. is formed on the surface of Si wiring in a semiconductor device. When an At wiring is formed on the interlayer insulation film through a contact hole drilled in the interlayer insulation film, molybdenum silicide, tungsten silicide, tantalum silicide, or titanium silicide is added to the contact area and under the d wiring. The present invention is characterized in that it is formed of a silicide film such as -ide, or a metal film such as molysodenum, tungsten, tantalum, or titanium.
第2図は、本発明による半導体装置の多層配線構造の一
実施例を示す断面図である。すなわち、si基板11の
表面に形r1ν゛された酸化膜12士にはS♂配線15
土にシリサイド膜14が形成された第1の配紳層が形成
され、層間絶縁膜15を介して層間絶縁膜15に開けら
れたコンタクト穴16を辿して、シリサイドまたはシリ
サイド膜14の構成金属からなる膜17が形成さり1、
該膜17上にはa膜18からなる配線が形成きれて成る
。FIG. 2 is a sectional view showing an embodiment of the multilayer wiring structure of a semiconductor device according to the present invention. That is, the S♂ wiring 15 is formed on the oxide film 12 formed on the surface of the Si substrate 11.
A first wiring layer in which a silicide film 14 is formed on soil is formed, and contact holes 16 made in the interlayer insulating film 15 are traced through the interlayer insulating film 15 to form silicide or the constituent metals of the silicide film 14. A film 17 consisting of 1,
A wiring made of the a film 18 is completely formed on the film 17.
上記発明の如く、下地si配線上のシリサイドと上部A
t配線下のシリサイドまたは金属膜とを圀続して形成す
ることにより、接続部の接触抵抗を小さくできる効果が
ある。上層配線がAtではな(EEcの場合にも本発明
が適用できることは云うまでもない。As in the above invention, the silicide on the underlying Si wiring and the upper A
Forming the silicide or metal film under the t-wiring in series has the effect of reducing the contact resistance of the connection portion. It goes without saying that the present invention is applicable even when the upper layer wiring is not At (EEc).
第1図は従来技術による半導体装fバの多層配線構造を
示す断面図、第2図d本発明の一実施例をテす半導体装
置の多層配線構造のn面図である。
1.11・・・・・・半導体基板
2.12・・・・酸化膜
5.16・・・・・・ Bi配線
4.15・−・・層間絶縁膜
5.16・・・・・コンタクト部
6.18・・・・・・Δを配線
14 ・・・・・シリサイド膜
17・・・・・シリサイド膜または金属膜以 十
出願人 株式会社 諏訪精工舎
代理人 弁理± 17)上 務FIG. 1 is a sectional view showing a multilayer wiring structure of a semiconductor device according to the prior art, and FIG. 2d is an n-side view of the multilayer wiring structure of a semiconductor device according to an embodiment of the present invention. 1.11...Semiconductor substrate 2.12...Oxide film 5.16...Bi wiring 4.15...Interlayer insulating film 5.16...Contact Part 6.18... Δ Wiring 14... Silicide film 17... Silicide film or metal film or more Applicant Suwa Seikosha Co., Ltd. Attorney ± 17) Superior Affairs
Claims (1)
ン・シリサイド、タンタル・シリサイドあるいけチタン
・シリサイド等のシリサイド膜が形成され、層間絶縁膜
に開けられたコンタクト穴を通して層間絶縁膜上にAt
配線を形成する場合に、コンタクト部及びa配線下には
モリブデン・シリサイド、タングステン・シリサイド、
タンタル拳シリサイドあるいけチタン・シリサイド等の
シリサイド膜か、あるいはモリブデン、タングステン、
タンタルあるいはチタン等の金属膜が形成されて成る事
を特徴とする半導体装置。A silicide film such as molybdenum silicide, tungsten silicide, tantalum silicide, or titanium silicide is formed on the surface of the Si wiring, and At is formed on the interlayer insulation film through a contact hole made in the interlayer insulation film.
When forming wiring, molybdenum silicide, tungsten silicide,
Tantalum silicide, silicide film such as titanium silicide, molybdenum, tungsten, etc.
A semiconductor device characterized by being formed with a metal film such as tantalum or titanium.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16541583A JPS6057646A (en) | 1983-09-08 | 1983-09-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16541583A JPS6057646A (en) | 1983-09-08 | 1983-09-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6057646A true JPS6057646A (en) | 1985-04-03 |
Family
ID=15811978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16541583A Pending JPS6057646A (en) | 1983-09-08 | 1983-09-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6057646A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4824801A (en) * | 1986-09-09 | 1989-04-25 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing aluminum bonding pad with PSG coating |
US4916397A (en) * | 1987-08-03 | 1990-04-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with bonding pad |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5360587A (en) * | 1976-11-11 | 1978-05-31 | Nec Corp | Production of semiconductor device |
JPS5649542A (en) * | 1979-09-28 | 1981-05-06 | Seiko Epson Corp | Integrated circuit device of mos type |
JPS5650536A (en) * | 1979-10-01 | 1981-05-07 | Seiko Epson Corp | Mos-type integrated circuit device |
-
1983
- 1983-09-08 JP JP16541583A patent/JPS6057646A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5360587A (en) * | 1976-11-11 | 1978-05-31 | Nec Corp | Production of semiconductor device |
JPS5649542A (en) * | 1979-09-28 | 1981-05-06 | Seiko Epson Corp | Integrated circuit device of mos type |
JPS5650536A (en) * | 1979-10-01 | 1981-05-07 | Seiko Epson Corp | Mos-type integrated circuit device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4824801A (en) * | 1986-09-09 | 1989-04-25 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing aluminum bonding pad with PSG coating |
US4916397A (en) * | 1987-08-03 | 1990-04-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with bonding pad |
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