JPS617655A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS617655A
JPS617655A JP59128231A JP12823184A JPS617655A JP S617655 A JPS617655 A JP S617655A JP 59128231 A JP59128231 A JP 59128231A JP 12823184 A JP12823184 A JP 12823184A JP S617655 A JPS617655 A JP S617655A
Authority
JP
Japan
Prior art keywords
pad
electrode
wiring
foundation
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59128231A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP59128231A priority Critical patent/JPS617655A/en
Publication of JPS617655A publication Critical patent/JPS617655A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce contact resistance between an Al pad and a foundation electrode by forming the foundation metal under the Al pad to a pad shape and connecting the Al pad and the foundation metal section in large areas. CONSTITUTION:An oxide film 12 is formed onto the surface of an Si substrate 11, and an electrode wiring 13 consisting of materials except an electrode, which is composed of Mo, etc. and contains Si, is shaped onto the film 12. The wiring 13 is connected to an Al pad 15 in large areas through an inter-layer insulating film 14 and a pad-section contact window 16. Accordingly, the wiring 13 is connected to a foundation electrode in large areas in the Al pad section, thus lowering contact resistance between the Al pad and the foundation electrode, then reducing the area of the layout of the pad section.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置におけるａ電極パッド部の構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to the structure of an a-electrode pad portion in a semiconductor device.

〔従来技術〕[Prior art]

従来、半導体装置に訃けるａバッド部構造Ｆｉ第１図に
示すごとき構造となっていた。すなわち、５ｆｆｌ基板
１の表面には酸化膜２が形成され、該酸化膜２上には多
結晶Ｂｉによる配線３が形成され、該多結晶Ｂｉ配線３
とａパッド５とけ層間絶縁膜４を介し、該層間絶縁膜４
に開けられたコンタクト穴６を通して接続されて成るの
が通例であった。Conventionally, a semiconductor device has a structure shown in FIG. That is, an oxide film 2 is formed on the surface of a 5ffl substrate 1, a wiring 3 made of polycrystalline Bi is formed on the oxide film 2, and a wiring 3 made of polycrystalline Bi is formed on the oxide film 2.
and the a pad 5 and the interlayer insulating film 4 through the interlayer insulating film 4.
Usually, the connection was made through a contact hole 6 drilled in the hole 6.

従来、上記の如く、多結晶Ｂｉ配線とａパッド部とは小
さなコンタクト穴を介して接続していた理由は、多結晶
ｓｉとＡｔパッドとを直接大面積で接続すると、多結晶
ｓｉのＦｊｉ成分がａパッド部に拡散し合金化し、ａパ
ｌドと全線あるいＦｉｐＪ、線との接続を困難にするか
らである。Conventionally, the reason why the polycrystalline Bi wiring and the a pad part were connected through a small contact hole as described above is that when the polycrystalline Si and At pad are directly connected over a large area, the Fji component of the polycrystalline Si This is because it diffuses into the a pad portion and forms an alloy, making it difficult to connect the a pad to the entire line or FipJ line.

しかし、上記従来技術によると、ａパッド部における下
地電極配線との接触面積が７ノーざく、接触抵抗が大と
なる共に、パッド部配線領域が大となり、高集積化に向
かないという欠点があった。However, according to the above-mentioned conventional technology, the contact area with the underlying electrode wiring on the a pad part is 7 points, which increases the contact resistance and the wiring area of the pad part becomes large, making it unsuitable for high integration. Ta.

〔目的〕〔the purpose〕

本発明は、かかる従来技術の欠点をなくし、ｄバッド部
配線面積の減少及び下地配線との接触抵抗の減少を計る
ことを目的とする。It is an object of the present invention to eliminate the drawbacks of the prior art and to reduce the wiring area of the d-pad portion and the contact resistance with the underlying wiring.

〔概要〕〔overview〕

上記目的を達成するための本発明の基本的な構成は、半
導体装置に於て、ａパッド２にけＭｏ等から成る下地電
極がパッド状に形成され、前記ａパッドと下地電極パッ
ド部とけ大面積で接続されて成ることを特徴とする。The basic structure of the present invention for achieving the above object is that, in a semiconductor device, a base electrode made of Mo or the like is formed on the a pad 2 in the shape of a pad, and the a pad and the base electrode pad portion have a large size. It is characterized by being connected by area.

〔実施例〕〔Example〕

以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.

第２図は本発明の一実施例を示す半導体装置の要部の平
面図と断面図である。すなわち、ｓｉ基板１１の表面に
は酸化膜１２が形成され、該酸化膜１２上にはＭＯ等か
ら成る多結晶Ｓｊ等ＳＺ’を含有する電極以外の材料か
ら成る電極配線１３が形成され該電極配線１３け眉間絶
縁膜１４を介して、　パッド部コンタクト窓１６を通し
て、ａパッード１５と大面積で接続されて成る。FIG. 2 is a plan view and a sectional view of essential parts of a semiconductor device showing an embodiment of the present invention. That is, an oxide film 12 is formed on the surface of the Si substrate 11, and an electrode wiring 13 made of a material other than the electrode containing SZ', such as polycrystalline Sj made of MO or the like, is formed on the oxide film 12. The wiring 13 is connected over a large area to the a-pad 15 through the glabellar insulating film 14 and through the pad contact window 16.

〔効果〕〔effect〕

上記の如く、ａパッド部に於て大面積で下地電極と接続
はれることにより、Ｕバッドと下地電・極との接触抵抗
が小さくなると共に、パッド部レイアウト面積が小ざく
てすむという効果がある。As mentioned above, by making a connection with the base electrode over a large area in the a pad part, the contact resistance between the U pad and the base electrode/pole is reduced, and the layout area of the pad part can be made small. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１１図（１０Ｌ）Ｆｉ従来技術による半導体装置のａ
パッド部の平面図、第１図の）は第１図れ）の断面図。 第２図Ｃａ、）ｆｉ本発明の一実施例を示す平面図、第
２図（６）は第１図（ロ））の断面図。 １．１１・・・・・・ｓｊ基板 ２．１２・・・・・・酸化膜 ３・・・・・・Ｓｊ配線 １３・・・・・・Ｍｏ配線 ４．１４・・・・・・層間絶縁膜 ５．１５・・・・・・ａパッド ６．１６・・・・・・コンタクト窓 板　　上FIG. 11 (10L) a of a semiconductor device according to Fi conventional technology
Fig. 1 is a plan view of the pad portion, and Fig. 1) is a sectional view of Fig. 1). Fig. 2(6) is a plan view showing an embodiment of the present invention, and Fig. 2(6) is a sectional view of Fig. 1(b). 1.11... Sj substrate 2.12... Oxide film 3... Sj wiring 13... Mo wiring 4.14... Interlayer Insulating film 5.15...A pad 6.16...Contact window plate top

Claims (2)

【特許請求の範囲】[Claims] （１）Ａｌパッド下には下地電極がパッド状に形成され
、前記Ａｌパッドと下地電極パッド部とは大面積で接続
されて成ることを特徴とする半導体装置。(1) A semiconductor device characterized in that a base electrode is formed in the shape of a pad under the Al pad, and the Al pad and the base electrode pad portion are connected over a large area. （２）下地電極をＭｏとなすことを特徴とする特許請求
範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the base electrode is made of Mo.
JP59128231A 1984-06-21 1984-06-21 Semiconductor device Pending JPS617655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59128231A JPS617655A (en) 1984-06-21 1984-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59128231A JPS617655A (en) 1984-06-21 1984-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS617655A true JPS617655A (en) 1986-01-14

Family

ID=14979733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59128231A Pending JPS617655A (en) 1984-06-21 1984-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS617655A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62274471A (en) * 1986-05-23 1987-11-28 Fanuc Ltd Picture processor
JPS63127382A (en) * 1986-11-18 1988-05-31 Fujitsu Ltd Inter-frame arithmetic unit
EP0844664A3 (en) * 1996-11-25 2000-05-10 Texas Instruments Incorporated A bond pad for an integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62274471A (en) * 1986-05-23 1987-11-28 Fanuc Ltd Picture processor
JPS63127382A (en) * 1986-11-18 1988-05-31 Fujitsu Ltd Inter-frame arithmetic unit
EP0844664A3 (en) * 1996-11-25 2000-05-10 Texas Instruments Incorporated A bond pad for an integrated circuit

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