JPS6054438A - Reversing and machining of ultrafine pattern - Google Patents
Reversing and machining of ultrafine patternInfo
- Publication number
- JPS6054438A JPS6054438A JP58163035A JP16303583A JPS6054438A JP S6054438 A JPS6054438 A JP S6054438A JP 58163035 A JP58163035 A JP 58163035A JP 16303583 A JP16303583 A JP 16303583A JP S6054438 A JPS6054438 A JP S6054438A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- pattern
- forming
- processed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003754 machining Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000009499 grossing Methods 0.000 claims 3
- 238000000059 patterning Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000003672 processing method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、微細・ｆターンの反転加工法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for reversing fine f-turns.
１１Ｃ来、素子領域の分離、配線の・リーニング等に所
謂フォトリソグラフィ技術が使用されている。ツメ］・
リングラフィ技術によれば、第１図（Ａ）に示す如く、
半導体基板１上に形成した被加工膜２上にレジスｉ・膜
３を形成する。次いで、レノスト膜３に同図（Ｂ）に示
す如く、開口部４を形成し、このレノスト膜３をマスク
にしてエツチング処理を施して液加二［膜２を設ける所
謂凹形・平ターン５の形成を行う。或は、同図（Ｃ）に
示す如く、レノスト膜３０所定領域だけを残存させ、こ
れをマスクにして被加工膜２にエツチング処理を施して
、新開凸形・やターン６の形成を行う。Since 11C, so-called photolithography technology has been used for separation of element regions, wiring/leaning, etc. Claw]・
According to phosphorography technology, as shown in Figure 1 (A),
A resist i/film 3 is formed on a film to be processed 2 formed on a semiconductor substrate 1. Next, as shown in FIG. 2B, an opening 4 is formed in the Lennost film 3, and an etching process is performed using the Lennost film 3 as a mask to form a so-called concave/flat turn 5 in which the film 2 is provided. Formation of Alternatively, as shown in FIG. 3C, only a predetermined region of the Renost film 30 remains, and using this as a mask, etching is performed on the film to be processed 2 to form a newly opened convex shape or turn 6.
このような凹形ノぐターン５の形成と凸形ノぐターン６
の形成では、前者の方が微細化が難しい。Formation of such a concave groove turn 5 and convex groove turn 6
The former is more difficult to miniaturize.
その理由は露光、現像のメカニズムにある。つまり、形
成する・臂ターンの太さは、露光量、現像１：で調整で
きるが、このときに微細なスペース（開口部）を形成し
ようとすると、薄い層のレジスト膜３の残りが発生する
問題がある。しかも、スに一スの幅（開口部の幅）のば
らつきが大きく、その制御が極めて雛しい。The reason lies in the mechanism of exposure and development. In other words, the thickness of the arm turn to be formed can be adjusted by adjusting the exposure amount and development 1:, but if you try to form a minute space (opening) at this time, a thin layer of resist film 3 will remain. There's a problem. Furthermore, the width of each slot (width of the opening) varies widely, and its control is extremely difficult.
本発明は、形状精度の高い微細パターンを高い再現性の
下に容易に形成することができる微細ノリ−ンの反転加
工法を提供するものである。The present invention provides a method for reversing a fine pattern by which a fine pattern with high shape accuracy can be easily formed with high reproducibility.
本発明は、開口部を有する所謂凹形・ぐターンのレノス
ト膜を極めて高い形状精度で形成することにより、形状
精度の高い微細・ぐターンを高い再現性の下に容易に形
成することができる微細ノ９ターンの反転加工法である
。The present invention makes it possible to easily form fine grooves with high shape accuracy and high reproducibility by forming a so-called concave groove-shaped Rennost film having openings with extremely high shape accuracy. This is a fine nine-turn reversal processing method.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
先ず、第２図（Ａ）に示す如く、シリコンからなる半導
体基板１θ上にチツ化シリコンからなる被加工膜２を、
例えば厚さ約１０００ＸまでＣ１Ｖ、Ｄ、（Ｃｈｅｍｉ
ｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）法にて
形成する。次いで、液加ｆ膜１１」二に二酸化ケイ累か
ら々る開１−１部形成用膜１２を厚さ約１０μｍまでＣ
，Ｖ、Ｉ）、法にて堆積する。次いで、開口部形成用膜
Ｉ２−１−に７９ｒ定パターンのレノスト膜１３を形成
［７、このレノスト膜１３をマスクにしフォトエツチン
グを施ｌ７．て開「１部形成用膜１２を・Ｐターニング
する。First, as shown in FIG. 2(A), a film to be processed 2 made of silicon oxide is placed on a semiconductor substrate 1θ made of silicon.
For example, C1V, D, (Chemi
It is formed by the cal vapor deposition method. Next, the film 12 for forming part 1-1 of the silicon dioxide film 11 is coated with carbon to a thickness of approximately 10 μm.
, V, I). Next, a 79r patterned Rennost film 13 is formed on the opening forming film I2-1- [7] Using this Rennost film 13 as a mask, photo-etching is performed 17. Then, turn the film 12 for forming one part.
次に、同図（８）に示す如く、レノス］・膜１３を除去
した後、開口部形成用膜１２を含む被加工膜１２土に、
レノスト膜１４を厚さ約１．５μｍ形成する。このレノ
スト膜１４の表面は、はぼ平坦に形成さＩｔ、−τいる
。Next, as shown in FIG. 8 (8), after removing the Renos film 13, the film 12 to be processed, including the film 12 for forming openings, is
A Lenost film 14 is formed to a thickness of about 1.5 μm. The surface of this Lennost film 14 is formed to be approximately flat.
次に、同図（Ｃ）にボ゛−４如く、レゾスト膜１４０表
向に非等方性エツチングであるＲ、１．Ｅ、（Ｒｅａｃ
ｔｉｖｅ Ｉｏｎ Ｆｅｔｃｈｉｎｇ ）処理を施し、
表面から約７０ （１０Ｘのところまで除去し、開口部
形成用膜１２を露出させｆｃ、 。次いで、同図の）に
示す如く、ＮＨ，Ｆ液によね開口部形成用膜１２を除去
し、Ｆ９［定の開ＩＴ−１、”ｉ ７ ｓをレジスト膜
１４に設ける。このレノスト膜１４をマスクにして湿式
エツチングを施し、被加工膜１）に所定の窓１６を開口
する。Next, as shown in FIG. 4 (C), the surface of the resist film 140 is anisotropically etched with R, 1. E, (Reac
tive Ion Fetching) treatment,
Remove about 70 (10X) from the surface to expose the opening forming film 12 fc. Then, as shown in the same figure, remove the opening forming film 12 by applying NH, F solution, F9 [certain opening IT-1, "i7s" is provided in the resist film 14. Using this Renost film 14 as a mask, wet etching is performed to open a predetermined window 16 in the film to be processed 1).
然る後、レノスト膜１４を除去して同図■）に示す如く
、所望の窓１６を有する被加工膜１１を半導体基板ＩＯ
上に残存せしめる。After that, the Lenost film 14 is removed, and the processed film 11 having the desired window 16 is placed on the semiconductor substrate IO, as shown in FIG.
Let it remain on top.
このようにこの微細・ぐターンの反転加工法によれば、
開口部形成用膜１２を用いることによって、レノスト１
１！４１４の露光作用、現像作用に左右されずに極めて
高い形状精度の下に、レノスト膜１４に開口部１５を設
けることができる。In this way, according to this fine pattern reversal processing method,
By using the opening forming film 12, Renost 1
The opening 15 can be provided in the Lenost film 14 with extremely high shape accuracy without being affected by the exposure action and development action of 1!414.
この開口部１５を有するレジスト膜１４をマスクにして
被加工膜１１の・平ターニングを行うので、良好な再現
性の下で被加工膜１ノに形状精度の高い微細・母ターン
を設けることができる。Since flat turning of the film to be processed 11 is performed using the resist film 14 having the openings 15 as a mask, it is possible to provide fine and master turns with high shape accuracy on the film to be processed 1 with good reproducibility. can.
以上説明した如く、本発明に係る微細ツヤターンの反転
加工法によれば、形状精度の高い微細・量ターンを高い
再現性の下に容易に形成できるものである。As explained above, according to the reversal processing method for fine glossy turns according to the present invention, fine and large turns with high shape accuracy can be easily formed with high reproducibility.
第１図（Ａｌ乃至同図（ｃｌ ｉ、、 、フォトリング
ラフィ技術による・にターン形成方法を示す説明図、第
２図（Ａ）乃至同図（ト））シＪ５、本発明方法を工８
１順に示す説明図である。
ＩＯ・・半導体基板、１ノ・・・液加］二膜、１２・・
・開口部形成用膜、１３・・・レゾスト膜、１４・・・
レノスＩ・１換、１５・・・開ｒ＋ １１〜．１６・・
・窓。FIG. 1 (Al to the same figure (cl i, , , explanatory diagram showing the method of forming a turn on the wafer by photolithography technology, FIG. 2 (A) to the same figure (G)) 8
It is an explanatory diagram shown in order. IO...Semiconductor substrate, 1...Liquid addition] Two films, 12...
- Opening forming film, 13...resist film, 14...
Renos I.1 conversion, 15...open r+ 11~. 16...
·window.
Claims (1)
部形成用膜をパターニングする工程と、該・平ターニン
グされた開口部形成用膜を含む前記被加工膜上に平滑用
膜を形成する工程と、該平滑用膜にエツチング処理を施
し前記開口部形成用膜を露出する工程と、前記開口部形
成用膜を除去して前記被加工膜の所定領域を露出する工
程と、残存した前記平滑用膜をマスクに該所定領域にエ
ツチング処理を施す工程とを具備することを特徴とする
微細・やターンの反転加工法。forming an opening forming film on the processed film; patterning the opening forming film; and forming a smoothing film on the processed film including the flat-turned opening forming film. a step of etching the smoothing film to expose the opening forming film; a step of removing the opening forming film to expose a predetermined region of the processed film; A method for reversing fine and small turns, comprising the step of etching the predetermined area using the remaining smoothing film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58163035A JPS6054438A (en) | 1983-09-05 | 1983-09-05 | Reversing and machining of ultrafine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58163035A JPS6054438A (en) | 1983-09-05 | 1983-09-05 | Reversing and machining of ultrafine pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6054438A true JPS6054438A (en) | 1985-03-28 |
Family
ID=15765943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58163035A Pending JPS6054438A (en) | 1983-09-05 | 1983-09-05 | Reversing and machining of ultrafine pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6054438A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331122A (en) * | 1986-07-24 | 1988-02-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS63129626A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Pattern formation |
-
1983
- 1983-09-05 JP JP58163035A patent/JPS6054438A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331122A (en) * | 1986-07-24 | 1988-02-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0624195B2 (en) * | 1986-07-24 | 1994-03-30 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| JPS63129626A (en) * | 1986-11-20 | 1988-06-02 | Fujitsu Ltd | Pattern formation |
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