JPH0624195B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming a contact hole in a semiconductor device.

[Conventional technology]

An outline of a method of forming a contact hole in a semiconductor device of this kind in a conventional example is shown in the order of steps in FIGS. 2 (a) and 2 (b).

The manufacturing process will be described with reference to these drawings of the conventional method.

First, after the element isolation insulating films 2a and 2b are selectively formed on the silicon semiconductor substrate 1 by a selective oxidation method or the like,
On the entire surface of the substrate surrounded by these element isolation insulation 2a, 2b,
The gate insulating film 3 is formed by a thermal oxidation method, etc.
Polycrystalline silicon is grown and deposited on the entire surface of this by a CVD (Chemical Vapor Daposition) method or the like, and the photolithography technique is used to selectively etch away this to form the gate electrode 4. Using the gate electrode 4 as a mask, the impurity diffusion regions 5a and 5b serving as the source and drain regions are formed on the semiconductor substrate 1 by the self-alignment method.
Are formed by diffusion (FIG. 2 (a)).

After that, BPSG (Bor
ophospho Silicate Glass) film 6 is grown and deposited (Fig.
(b)), and the BPSG film 6 was heat-treated at about 900 ° C. to flatten the surface (FIG. 6 (c)), and the flattened B
A patterned photoresist layer 7 is formed on the PSG film 6 by using a photoengraving technique (FIG. 2 (d)).

Then, by using the patterned photoresist layer 7 as a mask, anisotropic dry etching is performed to form the BPSG film.
6 is selectively etched to form contact holes 8 and 9a, 9b reaching the gate electrode 4 and the impurity diffusion regions 5a, 5b ((e) and (f) in the figure). Here,
During this etching, there is a step between the gate electrode 4 and the impurity diffusion regions 5a and 5b, and the positions in the depth direction at the contact holes 8 and 9a and 9b are different from each other. Therefore, while the contact holes 9a and 9b are formed by etching the BPSG film 6 and the gate insulating film 3 up to the impurity diffusion regions 5a and 5b at the deeper positions, the gates at the shallower positions are formed. In the electrode 4, the contact hole 8 is formed and the electrode surface portion is partially etched.

Then, the patterned photoresist layer 8 is removed by dry etching or the like, and heat treatment is performed at about 800 ° C. to remove each contact hole 8 in the BPSG film 6.
And 9a, 9b are inclined (Fig. (G)), and finally aluminum wirings 10 and 11a, 11b are formed in the respective contact holes 8 and 9a, 9b by the sputtering method. Figure (b)).

[Problems to be solved by the invention]

Thus, in the manufacturing method in the above-mentioned conventional example,
If there are two or more contact hole forming portions having different depths, the shallower contact hole forming portion may etch a part of the surface of the contact portion and damage the same surface portion. There was a problem to say.

The present invention has been made in order to solve such a conventional problem, and an object thereof is to mitigate damage caused by etching on a shallow side when forming contact holes having different depths. It is an object of the present invention to provide a method of manufacturing a semiconductor device of this type that is made possible.

[Means for solving problems]

In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention is characterized in that each contact portion formed on a semiconductor substrate having a step between them is passed through a first insulating film whose surface is flattened. When forming a contact hole, a second insulating film having a flattened surface having a larger etching rate than the first insulating film is formed on a semiconductor substrate including each contact portion, and a portion corresponding to the contact hole is left. Removing the second insulating film and forming a first insulating film having a surface planarized by including the remaining second insulating film, and forming the first and the first contact films corresponding to the contact holes. The first and second insulating films are etched with respect to the second insulating film until the second insulating film is removed under the condition that the etching rate of the second insulating film is large,
A contact hole can be formed in each contact portion.

[Work]

That is, in the method of the present invention, the etching rate of the second insulating film formed in the portion corresponding to the contact hole is
Make it larger than that of the first insulating film in other parts,
Since the first and second insulating films are etched until the second insulating film is removed, it is possible to mitigate the damage caused by etching the contact portions each having a step when the contact holes are etched. .

〔Example〕

An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS. 1 (a) to 1 (i).

FIGS. 1 (a) to 1 (j) are sectional views showing the method of this embodiment in the order of steps, and in these embodiment methods of FIGS. 1 (a) to 1 (j), FIGS. h) The same reference numerals as in the conventional method indicate the same or corresponding portions.

In this example method, first, similarly to the above-described conventional example method, the element isolation insulating films 2a and 2b and the gate insulating film 3 are formed on the silicon semiconductor substrate 1, and the gate electrode
4 and impurity diffusion region 5 to be the source and drain regions
Form a and 5b (Fig. 2 (a)).

After that, SOG (Spin
On Glass) film 12 is formed and heat-treated at about 900 ° C. to flatten the surface (FIG. 2 (b)).
A photoresist layer 13 patterned by using the photoengraving technique is formed on the upper surface of the photoresist layer 13 so as to correspond to a portion which will be a contact hole later (FIG. 2C).
With a mask as a wet or dry etching method,
The SOG film 12 is selectively removed by etching, that is, the SOG film 12 is left only in the portion corresponding to the contact hole (see FIG.
(d)).

Then, after removing the photoresist layer 13, a BPSG film 14 is grown and deposited on the entire surface by a CVD method or the like (FIG. 7E), and the BPSG film 14 is heat-treated at about 900 ° C. The surface is flattened (FIG. 6 (f)), and then wet etching is performed to remove the SOG film 12. In this case, the BPSG film 14 is left as a portion corresponding to the contact hole rather than the BPSG film 14. Since the etching rate of the SOG film 12 is very large, there is a step between the SOG film 12 and the impurity diffusion regions 5a and 5b as described above.
Even if the position of each of these contact parts is different in the depth direction, damage to the surface of the gate electrode 4 is sufficiently alleviated at this contact part at a shallower position, and the surroundings of the SOG film 12 itself. These gate electrodes 4 and impurity diffusion regions
Contact holes 8 and 9a, 9b reaching 5a, 5b can be easily formed ((g) and (h) in the same figure).

Further, after that, heat treatment at about 800 ° C. is performed in this state to make an appropriate inclination on each of the contact holes 8 and 9a, 9b of the BPSG film 14 (FIG. 2 (i)).
Finally, each contact hole 8
And aluminum wirings 10 and 11a, 11b are formed in the portions 9a, 9b (FIG. 11 (j)).

Therefore, according to the method of this embodiment, the contact portions having a step between them, that is, the contact hole forming portions for the gate electrode 4 and the impurity diffusion regions 5a and 5b, have the second etching rate large. Insulating film, in this case the SOG film 12 whose surface is flattened is left, and the first insulating film having a smaller etching rate than this is covered with the BPSG film 14 whose surface is flattened in this state. Etching up to the second insulating film, here the SOG film 12 whose surface is flattened, is performed by wet or dry etching with a contact hole to each target contact portion to prevent damage at the contact portion. It can be formed with sufficient relaxation.

〔The invention's effect〕

As described above in detail, according to the method of the present invention, in the case where contact holes are formed through the first insulating film whose surface is flattened in each contact portion having a step between them on the semiconductor substrate, each contact hole is formed. First, a second insulating film having a flattened surface having a larger etching rate than that of the first insulating film including the portion is formed, and the second insulating film is removed leaving a portion corresponding to the contact hole. Then, a first insulating film including the remaining second insulating film and having a flattened surface is formed, and further, a second insulating film of the second insulating film is formed on the first and second insulating films. Etching is performed until the second insulating film is removed under conditions such that the etching rate is increased so that contact holes can be formed in each contact portion. In the ring, as compared with the first insulating film, a large second insulating film etching rate,
Etching is removed as quickly as possible, and damage caused by etching of each contact portion having a step can be effectively and sufficiently alleviated, and the wet etching of each contact hole is Due to the presence of the insulating film, it has an excellent feature that the spread to the same surroundings can be reduced.

[Brief description of drawings]

1 (a) to 1 (j) are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG.
FIGS. 3A to 3H are cross-sectional views showing a manufacturing method according to the conventional example in the order of steps. 1 ・ ・ ・ Semiconductor substrate, 2a, 2b …… Element isolation insulating film, 3 ……
… Gate insulating film, 4 …… Gate electrode (contact part), 5a, 5b …… Impurity diffusion region (contact part),
8 and 9a, 9b ...... Contact holes, 10 and 11a, 11
b …… Aluminum wiring. 12 ... SOG film (second insulating film), 13 ... Photoresist layer, 14 ... BPSG film (first insulating film).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 29/784 (72) Inventor Junichi Arima 4-chome, Mizuhara, Itami City, Hyogo Mitsubishi Electric Corporation Kita Itami Works (72) Inventor Takeshi Noguchi 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation Kita-Itami Works (72) Inventor Masanori Obata 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Kitaitami Works Co., Ltd. Within

Claims (4)

[Claims] 1. A method of forming a contact hole in each contact portion having a step between them formed on a semiconductor substrate through a first insulating film whose surface is flattened. A step of forming a second planarized second insulating film having an etching rate higher than that of the first insulating film on a semiconductor substrate including: and the second insulating film leaving a portion corresponding to the contact hole. The step of removing the second insulating film, the step of forming the first insulating film having the surface planarized by including the remaining second insulating film, and the step of removing the second insulating film left in the contact hole corresponding portion. A step of etching the first insulating film and the second insulating film until they are removed so that a contact hole can be formed in each of the contact portions. Method of manufacturing location. 2. One of the contact portions has a gate electrode,
The method of manufacturing a semiconductor device according to claim 1, wherein the other is an impurity diffusion region. 3. The first insulating film is BPSG (Borophospho Silicat).
The e glass) film and the second insulating film are SOG (Spin On Glass) films, respectively.
A method of manufacturing a semiconductor device according to item. 4. The semiconductor device according to claim 1, 2, or 3, wherein the etching for the first and second insulating films is wet or dry etching. Production method.