JPH0774244A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH0774244A
JPH0774244A JP16300993A JP16300993A JPH0774244A JP H0774244 A JPH0774244 A JP H0774244A JP 16300993 A JP16300993 A JP 16300993A JP 16300993 A JP16300993 A JP 16300993A JP H0774244 A JPH0774244 A JP H0774244A
Authority
JP
Japan
Prior art keywords
insulating film
contact hole
film
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16300993A
Other languages
Japanese (ja)
Other versions
JP3350156B2 (en
Inventor
Masaaki Fujishima
正章 藤島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP16300993A priority Critical patent/JP3350156B2/en
Publication of JPH0774244A publication Critical patent/JPH0774244A/en
Application granted granted Critical
Publication of JP3350156B2 publication Critical patent/JP3350156B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To enhance step coverage at each contact hole while realizing fine patterning and high integration by forming a round shape corresponding to the depth of a contact hole above each contact hole without effecting round etching. CONSTITUTION:A first insulation film 5 applicable to reflow is formed thick on an underlying layer having level difference and a second insulation film applicable to reflow is formed relatively thin thereon. The second insulation film 6 is then etched back and contact holes 9A, 9B are made through an interlayer insulation film comprising the first and second insulation films 5, 6. Subsequently, the second insulation film 6 is reflow-processed through heat treatment thus forming a round shape corresponding to the depth of contact hole at the opening of contact hole.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に、段差を有する下地上に形成した層間絶縁
膜に、コンタクト孔を形成する半導体装置の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a contact hole is formed in an interlayer insulating film formed on a base having a step.

【0002】[0002]

【従来の技術】従来から、半導体装置の微細化及び高集
積化が進むにつれ、半導体装置の平坦化が益々重要にな
ってきている。そこで、半導体装置の平坦化を達成する
方法の一つとして、段差を有する下地上に形成した層間
絶縁膜を平坦化することが行われている。
2. Description of the Related Art Conventionally, as semiconductor devices have been miniaturized and highly integrated, planarization of semiconductor devices has become more and more important. Therefore, as one of methods for achieving flattening of a semiconductor device, flattening of an interlayer insulating film formed on a base having a step is performed.

【0003】この層間絶縁膜を平坦化する方法として
は、例えば、段差を有する下地上に、リフロー性を有す
る絶縁膜として、シリカフィルム等の無機系流動物やポ
リイミド系樹脂等の有機系流動物を塗布し、平坦な層間
絶縁膜を形成する方法、CVD(Chemical Vapor Depos
ition )法により、リフロー性を有する絶縁膜を堆積し
た後、これをエッチバックし、平坦な層間絶縁膜を形成
する方法等、種々の平坦化方法が紹介されている。
As a method for flattening the interlayer insulating film, for example, an inorganic fluid such as a silica film or an organic fluid such as a polyimide resin is used as an insulating film having a reflow property on a base having a step. Is applied to form a flat interlayer insulating film, CVD (Chemical Vapor Depos
ition) method, various flattening methods have been introduced, such as a method of depositing an insulating film having a reflow property and then etching it back to form a flat interlayer insulating film.

【0004】しかしながら、前記方法で層間絶縁膜の平
坦化を行うと、当該層間絶縁膜は、前記下地の段差に応
じて異なった膜厚を有した状態で形成される。従って、
前記層間絶縁膜にコンタクト孔を形成すると、当該層間
絶縁膜の膜厚が厚い部分(即ち、下地段差の谷の部分、
以下、『段差の谷部』という)に形成されるコンタクト
孔の深さが深くなり(高アスペクト比となり)、層間絶
縁膜の膜厚が薄い部分(即ち、下地段差の山の部分、以
下、『段差の山部』という)に形成されるコンタクト孔
の深さが浅くなるため、同一基板上に深さが異なったコ
ンタクト孔が共存していた。そして、前記深さが深いコ
ンタクト孔は、ステップカバレッジが悪く、また、リフ
ロー性を有する絶縁膜の膜厚も厚くなるため、その後の
工程で行う熱処理時に、該絶縁膜が流動してコンタクト
孔の開口部でオーバーハング形状となり、ステップカバ
レッジ特性を一層悪化させていた。
However, when the interlayer insulating film is flattened by the above method, the interlayer insulating film is formed in a state of having a different film thickness depending on the step of the underlying layer. Therefore,
When a contact hole is formed in the interlayer insulating film, a portion where the film thickness of the interlayer insulating film is large (that is, a valley portion of the underlying step,
Hereinafter, the depth of the contact hole formed in the "step valley" becomes deeper (higher aspect ratio), and the portion where the film thickness of the interlayer insulating film is thin (that is, the peak portion of the underlying step, hereinafter, Since the depth of the contact holes formed in "the stepped mountain portion") becomes shallow, contact holes having different depths coexisted on the same substrate. The deep contact holes have poor step coverage, and the thickness of the reflowable insulating film is large. Therefore, during heat treatment performed in a subsequent step, the insulating film flows and the contact holes The overhang shape was formed at the opening, further deteriorating the step coverage characteristic.

【0005】そこで、問題点を解決するため、従来で
は、深さの深いコンタクト孔に合わせて、全てのコンタ
クト孔の上部にラウンドエッチング(選択的な等方性エ
ッチング)を行い、当該コンタクト孔の上部をラウンド
形状とし、コンタクト孔のステップカバレッジを向上し
ていた。
Therefore, in order to solve the problem, conventionally, round etching (selective isotropic etching) is performed on the upper portions of all the contact holes in accordance with the deep contact holes to make the contact holes. The upper part has a round shape to improve the step coverage of the contact hole.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、前記深
さの深いコンタクト孔に合わせて、全てのコンタクト孔
の上部をラウンド形状にする従来例は、前記下地上に層
間絶縁膜を形成する際やコンタクト孔を形成する際に、
ラウンド形状を形成する際に失われる絶縁膜の幅を見込
んでラインアンドスペースを設計しなければならず、ま
た、深さの浅いコンタクト孔では、コンタクト孔が必要
以上に拡大する等、微細化及び高集積化に支障を来すと
いう問題があった。
However, according to the conventional example in which the upper portions of all the contact holes are rounded in accordance with the deep contact holes, the contact holes are formed when the interlayer insulating film is formed on the base or when the contact is formed. When forming the holes,
The line and space must be designed in consideration of the width of the insulating film that is lost when forming the round shape, and in the case of a contact hole with a shallow depth, the contact hole expands more than necessary, and miniaturization and There was a problem that it hindered high integration.

【0007】本発明は、このような従来の問題点を解決
することを課題とするものであり、ラウンドエッチング
を行うことなく、各々のコンタクト孔の上部に、各コン
タクト孔の深さに応じたラウンド形状を形成すること
で、コンタクト孔のステップカバレッジを向上すると共
に、微細化及び高集積化を達成した半導体装置の製造方
法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has an object to solve such a conventional problem, and it is possible to adjust the depth of each contact hole above each contact hole without performing round etching. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the step coverage of a contact hole is improved by forming a round shape and miniaturization and high integration are achieved.

【0008】[0008]

【課題を解決するための手段】この目的を達成するため
に、本発明は、段差を有する下地上に形成した層間絶縁
膜に、コンタクト孔を形成する半導体装置の製造方法に
おいて、前記段差を有する下地上にリフロー性を有さな
い第1の絶縁膜を厚く形成する第1工程と、当該第1の
絶縁膜上にリフロー性を有する第2の絶縁膜を、第1の
絶縁膜に対して相対的に薄く形成する第2工程と、当該
第2の絶縁膜の少なくとも一部が残留するように該第2
の絶縁膜をエッチバックし、前記第1の絶縁膜及び第2
の絶縁膜からなる層間絶縁膜を形成する第3工程と、当
該エッチバック終了後、当該層間絶縁膜にコンタクト孔
を開口する第4工程と、当該コンタクト孔開口後、熱処
理を行い前記第2の絶縁膜をリフローする第5工程と、
を含むことを特徴とする半導体装置の製造方法を提供す
るものである。
In order to achieve this object, the present invention provides a method of manufacturing a semiconductor device in which a contact hole is formed in an interlayer insulating film formed on a base having a step, the step having the step. A first step of thickly forming a first insulating film having no reflow property on the lower ground and a second insulating film having reflow property on the first insulating film with respect to the first insulating film. The second step of forming a relatively thin film, and the second step of forming the second insulating film so that at least a part of the second insulating film remains.
Of the first insulating film and the second insulating film are etched back.
A third step of forming an interlayer insulating film made of the insulating film, a fourth step of opening a contact hole in the interlayer insulating film after the etching back, and a heat treatment after opening the contact hole. A fifth step of reflowing the insulating film,
The present invention provides a method for manufacturing a semiconductor device including:

【0009】そして、前記第1の絶縁膜は、非添加硅酸
ガラスからなり、第2の絶縁膜は、硼硅燐酸ガラスから
なることを特徴とする半導体装置の製造方法を提供する
ものである。また、前記コンタクト孔開口後の第2の絶
縁膜は、最も厚い膜厚を有する領域における水平方向の
幅と当該膜厚との関係が、膜厚/水平方向の幅=0.6
以下となるように形成することを特徴とする半導体装置
の製造方法を提供するものである。
The first insulating film is made of non-doped silicate glass, and the second insulating film is made of borosilicate glass, which provides a method for manufacturing a semiconductor device. . In the second insulating film after the contact hole is opened, the relationship between the width in the horizontal direction in the region having the largest film thickness and the film thickness is: film thickness / width in the horizontal direction = 0.6.
The present invention provides a method for manufacturing a semiconductor device, which is formed as follows.

【0010】[0010]

【作用】本発明によれば、段差を有する下地上にリフロ
ー性を有さない第1の絶縁膜を厚く形成し、この上にリ
フロー性を有する第2の絶縁膜を相対的に薄く形成した
後、当該第2の絶縁膜の少なくとも一部が残留するよう
に該第2の絶縁膜をエッチバックし、前記第1の絶縁膜
及び第2の絶縁膜からなる層間絶縁膜を形成すること
で、前記段差の谷部には第2の絶縁膜を厚く形成され
る。従って、段差の山部には、第2の絶縁膜を薄く形成
するまたは除去した状態となる。そして、次に、前記層
間絶縁膜にコンタクト孔を開口した後、熱処理を行い前
記第2の絶縁膜をリフローすることで、当該第2の絶縁
膜の端部(コンタクト孔の開口上部近傍)の角は、ラウ
ンド形状化される。従って、ラウンドエッチングを行う
ことなく、コンタクト孔の上部にラウンド形状が形成さ
れる。この時、前記第2の絶縁膜のラウンド形状の径
は、当該第2の絶縁膜の膜厚が厚いほど大きくすること
ができるため、深さの深いコンタクト孔の開口部(ラウ
ンド形状)ほど大きく、深さが浅いコンタクト孔の開口
部(ラウンド形状)ほど小さくなる。このように、各々
のコンタクト孔の上部に、各コンタクト孔の深さに応じ
た最適な大きさのラウンド形状が、簡単に形成されるた
め、コンタクト孔のラウンドエッチによるラインアンド
スペースの設計を考慮する必要がない。
According to the present invention, the first insulating film having no reflow property is formed thick on the base having a step, and the second insulating film having reflow property is formed relatively thin on the first insulating film. After that, the second insulating film is etched back so that at least a part of the second insulating film remains, and an interlayer insulating film including the first insulating film and the second insulating film is formed. A second insulating film is thickly formed on the valley portion of the step. Therefore, the second insulating film is thinly formed or removed at the mountain portion of the step. Then, after a contact hole is opened in the interlayer insulating film, a heat treatment is performed to reflow the second insulating film, so that an end portion (near the opening of the contact hole) of the second insulating film is removed. The corners are rounded. Therefore, a round shape is formed above the contact hole without performing round etching. At this time, since the diameter of the round shape of the second insulating film can be increased as the film thickness of the second insulating film is increased, the diameter of the contact hole having a deeper depth (round shape) is increased. The shallower the depth (round shape) of the contact hole, the smaller the depth. In this way, a round shape with the optimum size according to the depth of each contact hole is easily formed on the top of each contact hole, so consider the line and space design by round etching of the contact hole. You don't have to.

【0011】そして、前記第1の絶縁膜としては、例え
ば、非添加硅酸ガラスからなる膜が挙げられ、第2の絶
縁膜としては、例えば、硼硅燐酸ガラスからなる膜が挙
げられる。また、前記コンタクト孔開口後の第2の絶縁
膜は、最も厚い膜厚を有する領域における水平方向の幅
とこの領域の膜厚との関係が、膜厚/水平方向の幅=
0.6以下となるように形成することで、前記作用をよ
り向上される。
The first insulating film may be, for example, a film made of non-doped silicate glass, and the second insulating film may be, for example, a film made of borosilicate glass. In the second insulating film after the opening of the contact hole, the relationship between the width in the horizontal direction in the region having the largest film thickness and the film thickness in this region is film thickness / width in the horizontal direction =
By forming it so as to be 0.6 or less, the above action can be further improved.

【0012】[0012]

【実施例】次に、本発明に係る実施例について、図面を
参照して説明する。図1ないし図5は、本発明の実施例
に係る半導体装置の製造工程の一部を示す部分拡大断面
図である。図1に示す工程では、フィールド酸化膜2に
より素子間分離された半導体基板1上に、ゲート酸化膜
3を形成した後、当該ゲート酸化膜3上及びフィールド
酸化膜2上に、ゲート電極形成材料である多結晶シリコ
ン膜を堆積し、これをパターニングしてゲート電極4を
形成する。このようにして、段差を有する下地を形成し
た。次に、前記ゲート電極4表面、ゲート酸化膜3及び
フィールド酸化膜2及び配線11上に、リフロー性を有
さない絶縁膜として、非添加硅酸ガラス(NSG;Non-
doped Silica Glass)膜を7000Å程度の膜厚で堆積
し、第1の絶縁膜5を形成する。次いで、前記第1の絶
縁膜5上に、リフロー性を有する絶縁膜として、硼硅燐
酸ガラス(BPSG;Boron-Phospho Silica Glass)膜
を6000Å程度の膜厚で堆積し、第2の絶縁膜6を形
成する。
Embodiments of the present invention will now be described with reference to the drawings. 1 to 5 are partial enlarged cross-sectional views showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention. In the step shown in FIG. 1, after a gate oxide film 3 is formed on a semiconductor substrate 1 which is element-isolated by a field oxide film 2, a gate electrode forming material is formed on the gate oxide film 3 and the field oxide film 2. Then, a polycrystalline silicon film is deposited and patterned to form a gate electrode 4. Thus, a base having a step was formed. Next, on the surface of the gate electrode 4, the gate oxide film 3, the field oxide film 2 and the wiring 11, as an insulating film having no reflow property, non-doped silicate glass (NSG;
A doped Silica Glass) film is deposited with a film thickness of about 7,000 Å to form the first insulating film 5. Then, a borosilicate glass (BPSG) film as a reflowable insulating film is deposited on the first insulating film 5 to a thickness of about 6000 Å, and the second insulating film 6 is formed. To form.

【0013】次に、図2に示す工程では、図1に示す工
程で得た第2の絶縁膜6上に、後に行うエッチバック工
程の際に使用する犠牲膜7を形成する。次いで、図3に
示す工程では、図2に示す工程で得た犠牲膜7をエッチ
バックし、露出した第2の絶縁膜6の一部をさらにエッ
チバックして該第2の絶縁膜6を平坦化する。この時、
前記第2の絶縁膜6は、該第2の絶縁膜6の最も厚い膜
厚bを有する領域において、後の工程で形成するコンタ
クト孔開口後の水平方向の幅aが、b/a=0.6以下
となるまでエッチバックし、下地段差の谷部に第2の絶
縁膜6を厚く、下地段差の山部に第2の絶縁膜6を薄く
形成した。このようにして、第1の絶縁膜5及び第2の
絶縁膜6からなる層間絶縁膜10を形成した。
Next, in the step shown in FIG. 2, a sacrificial film 7 to be used in the later etch back step is formed on the second insulating film 6 obtained in the step shown in FIG. Next, in the step shown in FIG. 3, the sacrificial film 7 obtained in the step shown in FIG. 2 is etched back, and a part of the exposed second insulating film 6 is further etched back to form the second insulating film 6. Flatten. At this time,
In the region of the second insulating film 6 having the thickest film thickness b, the second insulating film 6 has a horizontal width a after opening a contact hole formed in a later step, which is b / a = 0. Etching back was performed to 6 or less, and the second insulating film 6 was formed thick at the valley portion of the underlying step and thinned at the peak portion of the underlying step. In this way, the interlayer insulating film 10 including the first insulating film 5 and the second insulating film 6 was formed.

【0014】次に、図4に示す工程では、図3に示す工
程で形成した第2の絶縁膜6上に、フォトレジスト膜を
塗布し、これをパターニングしてコンタクト孔開口用の
レジストパターン8を形成する。次いで、前記レジスト
パターン8をマスクとして前記層間絶縁膜10及びゲー
ト酸化膜3に異方性エッチングを行いコンタクト孔9A
及び9Bを開口する。
Next, in the step shown in FIG. 4, a photoresist film is applied on the second insulating film 6 formed in the step shown in FIG. 3 and is patterned to form a resist pattern 8 for opening a contact hole. To form. Then, the interlayer insulating film 10 and the gate oxide film 3 are anisotropically etched by using the resist pattern 8 as a mask to form contact holes 9A.
And 9B are opened.

【0015】次いで、図5に示す工程では、図4に示す
工程で得たウエハに、800℃以上の温度で熱処理を行
い、前記第2の絶縁膜6をリフローさせ、コンタクト孔
9の上部をラウンド形状に開口する。この時、深さが深
いコンタクト孔9Aの上部側壁には、第2の絶縁膜6が
厚く形成されているため、開口径が大きいラウンド形状
が開口された。一方、深さが浅いコンタクト孔9Bの上
部側壁には、第2の絶縁膜6が薄く形成されているた
め、開口径が小さいラウンド形状が開口された。従っ
て、コンタクト孔の深さに応じて、ステップカバレッジ
特性を向上することができる最適な大きさの開口部を得
ることができる。
Next, in the step shown in FIG. 5, the wafer obtained in the step shown in FIG. 4 is heat-treated at a temperature of 800 ° C. or higher to reflow the second insulating film 6 and to cover the upper portion of the contact hole 9. Open in a round shape. At this time, since the second insulating film 6 is formed thick on the upper side wall of the contact hole 9A having a large depth, a round shape having a large opening diameter is opened. On the other hand, since the second insulating film 6 is thinly formed on the upper side wall of the contact hole 9B having a shallow depth, a round shape having a small opening diameter is opened. Therefore, it is possible to obtain an opening having an optimum size capable of improving the step coverage characteristic according to the depth of the contact hole.

【0016】その後、配線を形成する等、所望の工程を
行い、半導体装置を完成する。なお、本実施例では、第
1の絶縁膜5として、非添加硅酸ガラス(NSG)膜を
使用したが、これに限らず、絶縁性を有し且つリフロー
性を有さない膜であれば、他の絶縁膜を形成してもよ
い。また、本実施例では、第2の絶縁膜6として硼硅燐
酸ガラス(BPSG)膜を使用したが、これに限らず、
絶縁性を有し且つリフロー性を有した膜であれば、他の
絶縁膜を形成してもよい。
Thereafter, desired steps such as forming wiring are performed to complete the semiconductor device. In addition, in the present embodiment, a non-doped silicate glass (NSG) film is used as the first insulating film 5, but the present invention is not limited to this, as long as the film has an insulating property and does not have a reflow property. Alternatively, another insulating film may be formed. Further, in this embodiment, a borosilicate glass (BPSG) film is used as the second insulating film 6, but the second insulating film 6 is not limited to this.
Another insulating film may be formed as long as it has an insulating property and a reflow property.

【0017】[0017]

【発明の効果】以上説明したように、本発明に係る半導
体装置の製造方法は、下地段差の谷部にリフロー性を有
する第2の絶縁膜を厚く形成し、下地段差の山部に当該
第2の絶縁膜を薄く形成するまたは除去した状態の層間
絶縁膜を形成した後、これにコンタクト孔を開口し、次
いで、熱処理を行い前記第2の絶縁膜をリフローするた
め、当該第2の絶縁膜の端部(コンタクト孔の開口上部
近傍)の角をラウンド形状化することができる。従っ
て、ラウンドエッチングを行うことなく、コンタクト孔
の上部にラウンド形状を形成することができる。この
時、前記第2の絶縁膜のラウンド形状の径は、当該第2
の絶縁膜の膜厚が厚いほど大きくすることができるた
め、深さの深いコンタクト孔の開口部(ラウンド形状)
ほど大きく、深さが浅いコンタクト孔の開口部(ラウン
ド形状)ほど小さくすることができる。このため、各々
のコンタクト孔の上部に、各コンタクト孔の深さに応じ
た最適な大きさのラウンド形状を簡単に形成することが
できる。この結果、コンタクト孔のステップカバレッジ
を向上することができると共に、コンタクト孔のラウン
ドエッチによるラインアンドスペースの設計を考慮する
ことがないため、微細化及び高集積化を大幅に向上する
ことができる。
As described above, in the method of manufacturing a semiconductor device according to the present invention, the second insulating film having the reflow property is formed thick in the valley portion of the underlying step, and the second insulating film having the reflow property is formed in the mountain portion of the underlying step. After forming the interlayer insulating film in a state where the second insulating film is thinly formed or removed, a contact hole is opened in the interlayer insulating film, and then heat treatment is performed to reflow the second insulating film. The corner of the edge of the film (in the vicinity of the upper portion of the opening of the contact hole) can be rounded. Therefore, the round shape can be formed on the upper portion of the contact hole without performing the round etching. At this time, the round-shaped diameter of the second insulating film is
The thicker the insulating film, the larger the thickness of the insulating film.
The larger the contact hole is, the smaller the contact hole has a shallower depth (round shape). Therefore, it is possible to easily form the round shape having the optimum size according to the depth of each contact hole on the top of each contact hole. As a result, the step coverage of the contact hole can be improved, and since the line and space design by round etching of the contact hole is not taken into consideration, miniaturization and high integration can be significantly improved.

【0018】また、前記第2の絶縁膜は、最も厚い膜厚
を有する領域における水平方向の幅とこの領域の膜厚と
の関係が、膜厚/水平方向の幅=0.6以下となるよう
に形成することで、前記作用をより向上することができ
る。
In the second insulating film, the relation between the horizontal width in the region having the largest film thickness and the film thickness in this region is film thickness / horizontal width = 0.6 or less. By forming such a structure, the above-mentioned action can be further improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分拡大断面図である。
FIG. 1 is a partial enlarged cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the invention.

【図2】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分拡大断面図である。
FIG. 2 is a partial enlarged cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.

【図3】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分拡大断面図である。
FIG. 3 is a partial enlarged cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.

【図4】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分拡大断面図である。
FIG. 4 is a partial enlarged cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.

【図5】本発明の実施例に係る半導体装置の製造工程の
一部を示す部分拡大断面図である。
FIG. 5 is a partial enlarged cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the invention.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 フィールド酸化膜 3 ゲート酸化膜 4 ゲート電極 5 第1の絶縁膜 6 第2の絶縁膜 7 犠牲膜 8 レジストパターン 9A コンタクト孔 9B コンタクト孔 10 層間絶縁膜 11 配線 1 semiconductor substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 first insulating film 6 second insulating film 7 sacrificial film 8 resist pattern 9A contact hole 9B contact hole 10 interlayer insulating film 11 wiring

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 段差を有する下地上に形成した層間絶縁
膜に、コンタクト孔を形成する半導体装置の製造方法に
おいて、 前記段差を有する下地上にリフロー性を有さない第1の
絶縁膜を厚く形成する第1工程と、当該第1の絶縁膜上
にリフロー性を有する第2の絶縁膜を、第1の絶縁膜に
対して相対的に薄く形成する第2工程と、当該第2の絶
縁膜の少なくとも一部が残留するように該第2の絶縁膜
をエッチバックし、前記第1の絶縁膜及び第2の絶縁膜
からなる層間絶縁膜を形成する第3工程と、当該エッチ
バック終了後、当該層間絶縁膜にコンタクト孔を開口す
る第4工程と、当該コンタクト孔開口後、熱処理を行い
前記第2の絶縁膜をリフローする第5工程と、を含むこ
とを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising forming a contact hole in an interlayer insulating film formed on a stepped base, wherein a first insulating film having no reflow property is thickened on the stepped base. A first step of forming, a second step of forming a reflowable second insulating film on the first insulating film relatively thinly with respect to the first insulating film, and a second insulating step A third step of etching back the second insulating film so that at least a part of the film remains, and forming an interlayer insulating film composed of the first insulating film and the second insulating film, and ending the etch back. After that, a fourth step of opening a contact hole in the interlayer insulating film, and a fifth step of performing a heat treatment and reflowing the second insulating film after opening the contact hole are performed. Production method.
【請求項2】 前記第1の絶縁膜は、非添加硅酸ガラス
からなり、第2の絶縁膜は、硼硅燐酸ガラスからなるこ
とを特徴とする請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is made of non-doped silicate glass, and the second insulating film is made of borosilicate glass.
【請求項3】 前記コンタクト孔開口後の第2の絶縁膜
は、最も厚い膜厚を有する領域における水平方向の幅と
当該膜厚との関係が、膜厚/水平方向の幅=0.6以下
となるように形成することを特徴とする請求項1または
請求項2記載の半導体装置の製造方法。
3. The second insulating film after the opening of the contact hole has a relationship between the width in the horizontal direction and the film thickness in a region having the largest film thickness: film thickness / horizontal width = 0.6. The method of manufacturing a semiconductor device according to claim 1, wherein the method is formed as follows.
JP16300993A 1993-06-30 1993-06-30 Method for manufacturing semiconductor device Expired - Fee Related JP3350156B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16300993A JP3350156B2 (en) 1993-06-30 1993-06-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16300993A JP3350156B2 (en) 1993-06-30 1993-06-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0774244A true JPH0774244A (en) 1995-03-17
JP3350156B2 JP3350156B2 (en) 2002-11-25

Family

ID=15765465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16300993A Expired - Fee Related JP3350156B2 (en) 1993-06-30 1993-06-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3350156B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230142027A (en) 2022-03-30 2023-10-11 길벗 주식회사 Packaging film sealing machine for both pe and pvc film and shrinking packaging device for carbon fiber

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230142027A (en) 2022-03-30 2023-10-11 길벗 주식회사 Packaging film sealing machine for both pe and pvc film and shrinking packaging device for carbon fiber

Also Published As

Publication number Publication date
JP3350156B2 (en) 2002-11-25

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