JPS6045442U - リ−ドレスチツプキヤリア - Google Patents

リ−ドレスチツプキヤリア

Info

Publication number
JPS6045442U
JPS6045442U JP13809583U JP13809583U JPS6045442U JP S6045442 U JPS6045442 U JP S6045442U JP 13809583 U JP13809583 U JP 13809583U JP 13809583 U JP13809583 U JP 13809583U JP S6045442 U JPS6045442 U JP S6045442U
Authority
JP
Japan
Prior art keywords
chip carrier
leadless chip
package
leadless
signal pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13809583U
Other languages
English (en)
Inventor
清 桑原
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP13809583U priority Critical patent/JPS6045442U/ja
Publication of JPS6045442U publication Critical patent/JPS6045442U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来のリードレスチップキャリアをプリント基
板上に搭載接続した状態を示す断面説明図、第２図は本
考案によるリードレスチップキャリアを示す断面図、第
３図はプリント基板上に搭載接続して接続試験をしてい
る状態を示す断面説明図、第４図は本考案の変形例を示
す要部断面図である。 １′・・・・・・リードレスチップキャリア、２・・・
・・・回路チップ、３・・・・・・パッケージ、６・・
・・・・ボンディングワイヤ、７．１３・・・・・・パ
ターン、８・・・・・・ヴイア、９・・・・・・信号パ
ッド、１０・・・・・・ハンダボール、１１・・・・・
・プリント基板、１２・・・・・・接続パッド、１４・
・・・・・ブロービングパッド、１５・・・・・・改造
パッド、１８・・・・・・プローブ、１９・・・・・・
グランドパターン、２０・・・・・・リード線、２３・
・・・・・切断用パターン。

Claims (1)

    【実用新案登録請求の範囲】
  1. パッケージ内部に封止した回路チップとボンディングワ
    イヤで接続された信号パッドを該パッケージ裏面に複数
    個形成してなるリードレスチップキャリアにおいて、上
    記パッケージの側面に、上記信号パッドと導通されたブ
    ロービングパッドを設けたことを特徴とするリードレス
    チップキャリア。
JP13809583U 1983-09-06 1983-09-06 リ−ドレスチツプキヤリア Pending JPS6045442U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13809583U JPS6045442U (ja) 1983-09-06 1983-09-06 リ−ドレスチツプキヤリア

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13809583U JPS6045442U (ja) 1983-09-06 1983-09-06 リ−ドレスチツプキヤリア

Publications (1)

Publication Number Publication Date
JPS6045442U true JPS6045442U (ja) 1985-03-30

Family

ID=30309965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13809583U Pending JPS6045442U (ja) 1983-09-06 1983-09-06 リ−ドレスチツプキヤリア

Country Status (1)

Country Link
JP (1) JPS6045442U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152460A (ja) * 1991-11-26 1993-06-18 Kyocera Corp 半導体素子収納用パツケージ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152460A (ja) * 1991-11-26 1993-06-18 Kyocera Corp 半導体素子収納用パツケージ

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