JPS6044748B2 - ダイナミツクｍｏｓ記憶器に対する読出し増幅回路 - Google Patents
ダイナミツクｍｏｓ記憶器に対する読出し増幅回路Info
- Publication number
- JPS6044748B2 JPS6044748B2 JP52060391A JP6039177A JPS6044748B2 JP S6044748 B2 JPS6044748 B2 JP S6044748B2 JP 52060391 A JP52060391 A JP 52060391A JP 6039177 A JP6039177 A JP 6039177A JP S6044748 B2 JPS6044748 B2 JP S6044748B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- node
- circuit
- discharge
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000006870 function Effects 0.000 claims description 26
- 238000011156 evaluation Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000003321 amplification Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000007599 discharging Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000012854 evaluation process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 210000000352 storage cell Anatomy 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
- H03K3/356078—Bistable circuits using additional transistors in the feedback circuit with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356086—Bistable circuits with additional means for controlling the main nodes
- H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2623219.9 | 1976-05-24 | ||
| DE2623219A DE2623219B2 (de) | 1976-05-24 | 1976-05-24 | Verfahren zum Betreiben einer Leseverstärkerschaltung für einen dynamischen MOS-Speicher und Anordnung zur Durchführung dieses Verfahrens |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52144240A JPS52144240A (en) | 1977-12-01 |
| JPS6044748B2 true JPS6044748B2 (ja) | 1985-10-05 |
Family
ID=5978869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52060391A Expired JPS6044748B2 (ja) | 1976-05-24 | 1977-05-24 | ダイナミツクｍｏｓ記憶器に対する読出し増幅回路 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4119870A (enExample) |
| JP (1) | JPS6044748B2 (enExample) |
| DE (1) | DE2623219B2 (enExample) |
| FR (1) | FR2353116A1 (enExample) |
| GB (1) | GB1587129A (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4286178A (en) * | 1978-06-12 | 1981-08-25 | Texas Instruments Incorporated | Sense amplifier with dual parallel driver transistors in MOS random access memory |
| US4168490A (en) * | 1978-06-26 | 1979-09-18 | Fairchild Camera And Instrument Corporation | Addressable word line pull-down circuit |
| DE2839073C2 (de) * | 1978-09-07 | 1983-02-17 | Siemens AG, 1000 Berlin und 8000 München | Dynamische Stromquelle für Halbleiterbausteine und ihre Verwendung |
| US4543501A (en) * | 1978-09-22 | 1985-09-24 | Texas Instruments Incorporated | High performance dynamic sense amplifier with dual channel grounding transistor |
| US4255679A (en) * | 1978-10-30 | 1981-03-10 | Texas Instruments Incorporated | Depletion load dynamic sense amplifier for MOS random access memory |
| US4296335A (en) * | 1979-06-29 | 1981-10-20 | General Electric Company | High voltage standoff MOS driver circuitry |
| JPS6014438B2 (ja) | 1979-08-29 | 1985-04-13 | 株式会社東芝 | 不揮発性半導体メモリ− |
| US4421996A (en) * | 1981-10-09 | 1983-12-20 | Advanced Micro Devices, Inc. | Sense amplification scheme for random access memory |
| US4694205A (en) * | 1985-06-03 | 1987-09-15 | Advanced Micro Devices, Inc. | Midpoint sense amplification scheme for a CMOS DRAM |
| JPS62232796A (ja) * | 1986-04-01 | 1987-10-13 | Toshiba Corp | 半導体記憶装置 |
| EP0254980B1 (de) * | 1986-07-24 | 1991-09-25 | Siemens Aktiengesellschaft | Integrierbare Bewerterschaltung |
| US5519341A (en) * | 1994-12-02 | 1996-05-21 | Texas Instruments Incorporated | Cross coupled quad comparator for current sensing independent of temperature |
| US6882209B1 (en) * | 1997-09-09 | 2005-04-19 | Intel Corporation | Method and apparatus for interfacing mixed voltage signals |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE789500A (fr) * | 1971-09-30 | 1973-03-29 | Siemens Ag | Memoire a semiconducteurs avec elements de memorisation a un seul transistor |
| US3959781A (en) * | 1974-11-04 | 1976-05-25 | Intel Corporation | Semiconductor random access memory |
| US4004284A (en) * | 1975-03-05 | 1977-01-18 | Teletype Corporation | Binary voltage-differential sensing circuits, and sense/refresh amplifier circuits for random-access memories |
| US3978459A (en) * | 1975-04-21 | 1976-08-31 | Intel Corporation | High density mos memory array |
| US3993917A (en) * | 1975-05-29 | 1976-11-23 | International Business Machines Corporation | Parameter independent FET sense amplifier |
| US4025907A (en) * | 1975-07-10 | 1977-05-24 | Burroughs Corporation | Interlaced memory matrix array having single transistor cells |
| US4061999A (en) * | 1975-12-29 | 1977-12-06 | Mostek Corporation | Dynamic random access memory system |
| US4028557A (en) * | 1976-05-21 | 1977-06-07 | Bell Telephone Laboratories, Incorporated | Dynamic sense-refresh detector amplifier |
-
1976
- 1976-05-24 DE DE2623219A patent/DE2623219B2/de active Granted
-
1977
- 1977-05-19 US US05/798,431 patent/US4119870A/en not_active Expired - Lifetime
- 1977-05-20 FR FR7715513A patent/FR2353116A1/fr active Granted
- 1977-05-23 GB GB21585/77A patent/GB1587129A/en not_active Expired
- 1977-05-24 JP JP52060391A patent/JPS6044748B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1587129A (en) | 1981-04-01 |
| JPS52144240A (en) | 1977-12-01 |
| FR2353116A1 (fr) | 1977-12-23 |
| US4119870A (en) | 1978-10-10 |
| DE2623219C3 (enExample) | 1979-06-13 |
| DE2623219B2 (de) | 1978-10-12 |
| DE2623219A1 (de) | 1977-12-01 |
| FR2353116B1 (enExample) | 1984-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6044748B2 (ja) | ダイナミツクｍｏｓ記憶器に対する読出し増幅回路 | |
| JPS60694A (ja) | 半導体メモリ | |
| JPH0335751B2 (enExample) | ||
| US5388078A (en) | Semiconductor memory device having current to voltage conversion type amplifier | |
| JPH0334150B2 (enExample) | ||
| US4414515A (en) | CR Oscillator having constant current charging source | |
| US4239991A (en) | Clock voltage generator for semiconductor memory | |
| EP0168246A2 (en) | Improved active pull-up circuit | |
| US6233186B1 (en) | Memory device having reduced precharge time | |
| US4736343A (en) | Dynamic RAM with active pull-up circuit | |
| US4379345A (en) | Dynamic read amplifier for metal-oxide-semiconductor memories | |
| JPS6044749B2 (ja) | Ｍｏｓ記憶器に対する関数発生器 | |
| US4460983A (en) | Integrated dynamic read-write memory | |
| US6901019B2 (en) | Sense amplifier with adaptive reference generation | |
| US4897559A (en) | Variable clock delay circuit utilizing the R-C time constant | |
| US5153467A (en) | Bootstrap circuit for word line driver in semiconductor memory | |
| JPH0245275B2 (enExample) | ||
| JPH04212783A (ja) | メモリバスのプリチャージ回路 | |
| JP3167323B2 (ja) | ダイナミック半導体メモリ | |
| JPS599735A (ja) | クロツク発生回路 | |
| US6404273B1 (en) | Voltage booster with a low output resistance | |
| JPS5842558B2 (ja) | アドレス バッファ回路 | |
| US4565933A (en) | Circuit for generating rapid pulses | |
| JP2797837B2 (ja) | ブースト電位発生回路 | |
| JP2557871B2 (ja) | 半導体装置 |