JPS60244035A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS60244035A
JPS60244035A JP59099228A JP9922884A JPS60244035A JP S60244035 A JPS60244035 A JP S60244035A JP 59099228 A JP59099228 A JP 59099228A JP 9922884 A JP9922884 A JP 9922884A JP S60244035 A JPS60244035 A JP S60244035A
Authority
JP
Japan
Prior art keywords
wiring layer
insulating material
lead frame
resin
rubber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59099228A
Other languages
English (en)
Inventor
Masaru Nakagaki
勝 中垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59099228A priority Critical patent/JPS60244035A/ja
Publication of JPS60244035A publication Critical patent/JPS60244035A/ja
Pending legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 −１−、−へ 本発明は半導体装置の製造方法に係わり、特ＫＩＣ（集
積回路）アセンブリ工程のワイヤボンディング方法に関
する。
〔発明の技術的背景とその問題点〕
従来のワイヤがンディングは、グラスチックｒｃを例と
すると、第１図に示すようにリードフレーＡＪ、チッｆ
２間を金属ワイヤ３でデンディングし、その徒弟２図に
示すように樹脂４で封止するものであった。図中５はデ
ンディングパッド、６はがンディング台である。
しかしながら上記従来のワイヤボンディング方法では、
リードフレーム１とチッｆ；ｔｏ接続に金属ワイヤ３を
使用するが、ポンディングパッド５のサイズ、コストの
面でワイヤ３を太くできず、この部分が弱くなる。また
樹脂４で封止する際、ワイヤ３がリードフレーム１側と
チップ２側の両端以外はどこにも非接触なため、樹脂に
ワイヤ３が流される。このため樹脂４の封止速度が遅く
なる。またワイヤ３に金属を使用するため、ポンディン
グ速度に限度があシ、２− また１本ずつ行なうため、多ピン（端子）になればなる
ほど生産性が劣るものであった。また温度サイクルテス
トの際、樹脂４の伸縮を直接４レット２．ワイヤ３に受
けるので、そのダメージによりワイヤ切れ、ペレットク
ラック等を起こしやすいものであった。
〔発明の目的〕
本発明は上記実情に鑑みてなされたもので、ＩＣのアセ
ンブリ工程のスビードアッゾを図シ、かつその信頼性を
高めることができる半導体装置の製造方法を提供しよう
とするものである。
〔発明の概要〕
本発明は上記目的を達成するため、マスキングによシ、
リードフレームとチップとの間に弾性を有する絶縁物を
塗布により形成し、該絶縁物上に前記チップのノヤツド
と前記リードフレームが接続されるように導電性を有す
る配線層を塗布によ多形成したものである。
〔発明の実施例〕 以下図面を参照して本発明の一実施例を説明する。第３
図〜第５図は同実施例の工程説明図であるが、これは構
成を前記従来のものと対応させた場合の例であるから、
対応個所には同一符号を用いる。第３図に示されるよう
にマスク１１でリードフレーム１及びチップ２のパッド
５をマスクし、グル状の絶縁物１２を吹き付は等により
塗布する。この絶縁物１２については、例えばＪＣＲ等
シリコーンゴムを使用できる。次に絶縁物１２を加熱等
によシゴム状に硬化させる。次に第４図に示すように配
線になり得る部分以外にマスク１３を施こし、導電物１
４を吹き付は等により塗布し、絶縁物１２上にパッド５
とリードフレーム１が接続されるように配線層を形成す
る。上記導電物（配線層）１４については、例えばゴム
系樹脂に銀などの導電体を添加したものを使用できる。
次に第５図に示す如く樹脂４により封止を行なうもので
ある。
上記の如き工程によれば、マスク塗布によシ、全ビン（
端子）同時に配線でき、配線１４のプリント化を行なっ
たため、特に多ビンのＩＣに対し能率がよい。また配線
１４に、宙に浮いたような非接触な個所がないため、従
来のようにワイヤ流れ等が生じる心配がなく、封止の際
樹脂４の流入速度を速くできる。またチッｆ２上及び周
りに、弾性を有する絶縁物１２を設けるため樹脂４から
のダメージが少なく、大型チップのクラックに対し有効
である。
第６図は本発明の他の実施例で、時計、電卓用パッケー
ジに本発明を応用したものである。
これはプリント配線２１を施こしたガラスエポキシ基板
２２上に、前実施例の構成を設けたものであるから、同
一個所には同一符号を付して説明を省略する。
〔発明の効果〕
以上説明した如く本発明によれば、ＩＣのアセンブリ工
程のス♂−ドアｙノ化を図り、かつその信頼性を高める
ことができるものである。
【図面の簡単な説明】
第１図、第２図は従来のＩＣのアセンブリ工程図、第３
図ないし第５図は本発明の一実施例の工程説明図、第６
図は本発明の他の実施例の説明図である。 １・・・リードフレーム、２・・・チップ、４・・・樹
脂、５・・・ノやラド、１１　、１３・・・マスク、１
２・・・絶縁物、１４・・・配線層。 出願人伏理人　弁理士　鈴　江　武　彦第１図 ３ 第３図 １

Claims (3)

    【特許請求の範囲】
  1. （１）　マスキングにより、リードフレームとチップと
    の間に絶縁物を塗布によ多形成し、該絶縁物上に前記チ
    ップのパッドと前記リードフレームが接続されるように
    導電性を有する配線層を塗布によ〕形成したことを特徴
    とする半導体装置の製造方法。
  2. （２）前記絶縁物の塗布は、吹き付は可能な絶縁物を吹
    き付けることにより行なうものであることを特徴とする
    特許請求の範囲第１項に記載の半導体装置の製造方法。
  3. （３）前記配線層の塗布は、吹き付は可能な導電物を吹
    き付けることにより行なうものであることを特徴とする
    特許請求の範囲第１項に記載の半導体装置の製造方法。
JP59099228A 1984-05-17 1984-05-17 半導体装置の製造方法 Pending JPS60244035A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59099228A JPS60244035A (ja) 1984-05-17 1984-05-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59099228A JPS60244035A (ja) 1984-05-17 1984-05-17 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS60244035A true JPS60244035A (ja) 1985-12-03

Family

ID=14241809

Family Applications (1)

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JP59099228A Pending JPS60244035A (ja) 1984-05-17 1984-05-17 半導体装置の製造方法

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146769U (ja) * 1984-08-30 1986-03-28 日本電信電話株式会社 電子回路形成チツプ搭載装置
US5175060A (en) * 1989-07-01 1992-12-29 Ibiden Co., Ltd. Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
JP2002231736A (ja) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Ｉｃチップを実装したアンテナの形成方法
JP2007510301A (ja) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド 部品の電気的接続
US7230341B2 (en) 2003-03-13 2007-06-12 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
JP2015012165A (ja) * 2013-06-28 2015-01-19 富士機械製造株式会社 回路機器製造方法および、成形用の型

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146769U (ja) * 1984-08-30 1986-03-28 日本電信電話株式会社 電子回路形成チツプ搭載装置
US5175060A (en) * 1989-07-01 1992-12-29 Ibiden Co., Ltd. Leadframe semiconductor-mounting substrate having a roughened adhesive conductor circuit substrate and method of producing the same
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
JP2002231736A (ja) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Ｉｃチップを実装したアンテナの形成方法
JP4666296B2 (ja) * 2001-01-31 2011-04-06 トッパン・フォームズ株式会社 Ｉｃチップを実装したアンテナの形成方法
US7230341B2 (en) 2003-03-13 2007-06-12 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
US7564142B2 (en) 2003-03-13 2009-07-21 Seiko Epson Corporation Electronic device and method of manufacturing the same, circuit board, and electronic instrument
JP2007510301A (ja) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド 部品の電気的接続
JP2015012165A (ja) * 2013-06-28 2015-01-19 富士機械製造株式会社 回路機器製造方法および、成形用の型

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