TW402795B - Semiconductor device capable of avoiding the offset of the wire and its manufacturing method - Google Patents

Semiconductor device capable of avoiding the offset of the wire and its manufacturing method Download PDF

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Publication number
TW402795B
TW402795B TW088101268A TW88101268A TW402795B TW 402795 B TW402795 B TW 402795B TW 088101268 A TW088101268 A TW 088101268A TW 88101268 A TW88101268 A TW 88101268A TW 402795 B TW402795 B TW 402795B
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Taiwan
Prior art keywords
fixing portion
wires
substrate
wafer
semiconductor device
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TW088101268A
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Chinese (zh)
Inventor
Tai-Chun Huang
Chun-Hung Lin
Su Tao
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

This invention relates to a semiconductor device capable of avoiding the offset of the wire and its manufacturing method. The semiconductor device comprises a substrate, a die, a plurality of conductive wires and a fixing portion. The die is disposed on the surface of the substrate. The plurality of conductive wires are connected with a plurality of solder pad on the upper surface of the substrate and with a plurality of solder pad on the upper surface of the die. The fixing portion circles on the peripheral of the die and overlaps the middle portion of a plurality of conductive wires. Due to the sweep of the middle portion of conductive wires, the contact in between the conductive wires can be easily caused. Then, the encapsulation is injected on the die and the conductive wires to form a encapsulating body.

Description

403795 五、發明說明（1) 發明領域 本發明係有關於一種防止晶片引線偏移之半導體裝置及 其製法’特別是在封裝基板上之晶片或電子元件進行封裝 時’在晶片或電子元件之導線區域設置一固定部之之半導 體裝置及其製法。 先前技術 習用之晶片或電子元件與基板打線後進行注膠時，由於 封膠趙之黏滯力衝線〔s w e e p〕使導線與導線之間接觸而 形成一通路，因此，當該晶片或電子元件運作時，該晶片 或電子元件之導線造成短路〔sh〇rt〕而使該晶片或電子 元件失去作用或損壞。因此，將導線必須絕緣隔離固定， 以避免晶片或電子元件之導線造成短路。 習用技術中，如1998年12月11日公告之我國專利公告第/ 347573號所揭示之積體電路晶片引線之保護方法〔如第 圖所示〕，其未進行灑膠時’主要將一晶片U被一基板1〇· 所承載，並有許多引線12從該晶片向外延引連接至該基板 。如第二圖所示，進行灑膠時’藉散佈膠13於該引線12部 份以縮短該引線外露之線弧長度，其中該膠1 3點灑於該。曰 人曰曰 片11上，如第三圖所示之擴散膠時，該膠13向外流動擴散 後覆蓋引線1 2。按’該發明專利所揭示之保護方法，其中 膠1 3點灑於晶片11上並向外流動擴散後覆蓋引線1 2，因此 ，該晶片11及部份引線12被膠13所覆蓋，而該膠13由晶片 11向外流動擴散及硬化需要非常長時間。 另一習用技術中’如1994年7月19日頒予Primeaux之美403795 V. Description of the invention (1) Field of the invention The present invention relates to a semiconductor device for preventing chip lead deviation and a manufacturing method thereof 'especially when packaging a chip or an electronic component on a packaging substrate' in a chip or electronic component wire A semiconductor device with a fixed portion and a manufacturing method thereof are provided in the area. When the wafer or electronic component used in the prior art is glued after the substrate is wired, the adhesive seal sweep makes a path between the wire and the wire. Therefore, when the chip or electronic component is connected, a path is formed. During operation, the wires of the chip or electronic component cause a short circuit [short] and the chip or electronic component becomes ineffective or damaged. Therefore, the wires must be insulated and fixed to avoid short circuits caused by the wires of the chip or electronic components. In conventional technology, such as the method of protecting integrated circuit chip leads disclosed in Chinese Patent Bulletin No. 347573 published on December 11, 1998 [as shown in the figure], when the glue is not sprayed, 'mainly a chip U is carried by a substrate 10 ·, and there are many leads 12 extending from the wafer to the substrate. As shown in the second figure, when the glue is sprayed ', the glue 13 is spread on the lead 12 to shorten the exposed arc length of the lead, where the glue is sprinkled at 13 points. On the sheet 11, when the diffusion glue is shown in the third figure, the glue 13 flows outward and diffuses, and then covers the leads 12. According to the protection method disclosed in the invention patent, the glue 13 is sprinkled on the wafer 11 and spreads out to cover the leads 12. Therefore, the wafer 11 and part of the leads 12 are covered by the glue 13, and the It takes a very long time for the glue 13 to flow outward and diffuse and harden from the wafer 11. Another conventional technique ’such as the beauty awarded to Primeaux on July 19, 1994

408795408795

國專利第5, 331，205號所揭示塑膠封裝之導線保護。請參 照第四囷所不，其主要包含一第一封膠體2〇、一第二封膠 體21、一晶片23、數條導線24及一導線架25，該導線架25 ^有一晶片塾22及另包含數個接腳，而該晶片23設有數個 ，墊並該晶㈣被置於該晶片㈣±，該數條導線24則將 =片23之焊墊連接至導線架25之接腳。該第一封膠體⑼係 ，，熱膨脹係數材料形成，該第一封膠體2〇覆蓋晶片23之 面及包覆每一導線24。該第二封膠體21包覆整個晶片 ，-部份導線架25。按’該發明專利案所揭示之保護體 ’其中第-封膠體20覆蓋晶片23之上表面及包覆每一導線 因此，該第一封膠體2〇硬化需要非常長時間。 有鑑於此，本發明之防止導線偏移之封膠體改良上述缺 點，在，板表面位於導線區域之局部區域上設置一固定部 I特!!疋在注膠口附近容易造成衝線之處設置一固定部，< 〜該線避免衝線，由於本發明在局部導線區域設置一固 疋Ρ而減ν固疋部之材料使用量且縮短該固定部硬化時間 ^ Λ 本發明具有知省時間之功效。此外，本發明之固 从覆蓋於晶片上’以避免由不同膨脹係數所造成的應 變力作用於該晶片上。 發明概要 奘番甘制要目的係提供一種防止晶片引線偏移之半導趙 、製法’在局部導線區域上設置表面設置一固定部 該固定部硬化時間，使其具有節省固定部硬化時間National Patent No. 5,331,205 discloses the protection of the wires of a plastic package. Please refer to the fourth example, which mainly includes a first encapsulant 20, a second encapsulant 21, a wafer 23, a plurality of wires 24, and a lead frame 25. The lead frame 25 has a wafer 22 and In addition, it includes a plurality of pins, and the chip 23 is provided with a plurality of pads, and the wafer is placed on the wafer ㈣ ±, and the plurality of wires 24 connect the pads of the chip 23 to the pins of the lead frame 25. The first sealing compound is formed of a material having a thermal expansion coefficient. The first sealing compound 20 covers the surface of the wafer 23 and covers each wire 24. The second encapsulant 21 covers the entire wafer, a portion of the lead frame 25. According to the "protective body disclosed in this invention patent case", wherein the first-sealing gel 20 covers the upper surface of the wafer 23 and covers each wire. Therefore, it takes a very long time for the first-sealing gel 20 to harden. In view of this, the sealing glue of the present invention for preventing the displacement of the wire improves the above-mentioned disadvantages. A fixed part I is provided on a local area of the board surface located on the wire area !! A fixed part, < ~ The line avoids punching, because the present invention sets a solid wire in the local wire area to reduce the material usage of the solid part and shorten the hardening time of the fixed part ^ Λ The invention has time-saving knowledge Effect. In addition, the present invention covers the wafer 'to prevent strain forces caused by different expansion coefficients from acting on the wafer. Summary of the invention The main purpose of the system is to provide a semi-conductor to prevent the chip lead from shifting. The method is to provide a fixed part on the surface of a part of the wire area. The fixed part has a hardening time so that it can save the fixed part hardening time.

第5頁 402785 (3) 五、發明說明 本發明次要目的係提供一種防止晶片引線偏移之半導艎 裝置及其製法’該固定部未覆蓋於晶片上，以避免由不同 膨服係數所造成的應變力作用於該晶片上。同時可使封膠 時不必考慮引線偏移’而具有可選擇採用不同條件〔封膠 參數〕之封膠之功效。 f據本發明，其製法係在基板上表面晶片邊緣之數個導 線區形成一固定部’再等該固定部硬化形成一絕緣分隔固 定體’該固定部硬化後在該晶片及導線上注入封膠形成一 封膠體。本發明一較佳實施例主要包含一基板、一晶片或 電子元件、數條導線及一固定部，該基板之上表面上置該 晶片或電子元件，該數條導線則連接該基板上表面之數個 焊墊及該晶片上表面之數個焊墊。該固定部環繞於晶片之 周緣並包覆數條導線之主要部份，該數條導線之主要部 位於導線之中段，該導線中段因衝線而容易產生導線之$ 接觸°本發明另一較佳實施例主要包含一基板、一晶片或 電子元件、數條導線、一第一固定部及一第二固定部，該 基板之上表面上置該晶片或電子元件，該數條導線則連接 該基板上表面之數個焊墊及該晶片上表面之數個焊塾。該 第一固定部位於最容易造成導線衝線之注膠口附近之基^ 表面上，而該第二固定部位於次容易造成導線衝線之主 口相對角落附近之基板表面上。 由於本發明以固定部將設置於非晶片上表面之晶片周圍 ，注膠口附近局部導線區域，將導線中段適當絕緣隔離固 定’使其具有節省固定部硬化時間之功效。此外，該固定Page 5 402785 (3) V. Description of the invention The secondary object of the present invention is to provide a semiconducting device and a method for preventing wafer leads from shifting. The fixing portion is not covered on the wafer to avoid being affected by different expansion coefficients. The resulting strain forces act on the wafer. At the same time, the sealant can be used without having to consider the lead offset ', and has the effect of selecting sealants with different conditions [sealant parameters]. f According to the present invention, the manufacturing method is to form a fixing portion 'on a plurality of lead areas on the edge of the wafer on the substrate', and then wait for the fixing portion to harden to form an insulating partition fixing body. The gel forms a colloid. A preferred embodiment of the present invention mainly includes a substrate, a wafer or an electronic component, a plurality of wires, and a fixing portion. The wafer or the electronic component is disposed on an upper surface of the substrate, and the plurality of wires are connected to the upper surface of the substrate. A plurality of pads and a plurality of pads on the upper surface of the wafer. The fixed part surrounds the periphery of the chip and covers the main part of the plurality of wires. The main part of the plurality of wires is located in the middle part of the wire. The middle part of the wire is prone to make contact with the wire due to punching. The preferred embodiment mainly includes a substrate, a wafer or electronic component, a plurality of wires, a first fixing portion and a second fixing portion. The wafer or the electronic component is placed on the upper surface of the substrate, and the plurality of wires are connected to the Several pads on the upper surface of the substrate and several pads on the upper surface of the wafer. The first fixing portion is located on the surface of the substrate near the injection port where the wire punching is most likely to occur, and the second fixing portion is located on the surface of the substrate near the opposite corner of the main port where the wire punching is most likely to occur. Because the present invention uses the fixing part to be arranged around the wafer other than the upper surface of the wafer, and the local wire area near the injection port, the middle section of the wire is properly insulated and fixed, so that it has the effect of saving the hardening time of the fixing part. Also, the fix

—4027的 五、發明說明（4) --- 部未覆蓋於晶片上’以避免由不同膨脹係數所造成的應變 力作用於該晶片上。 圖式說明 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵，下文特舉本發明較佳實施例，並配合所附圖式， 作詳細說明如下。 第1圖：習用我國公告第3475 73號半導體封裝構造未進 行灑膠之示意圖； 第2圖：習用我國公告第347573號半導體封裝構造進行 灑膠之示意圖； 第3圖：習用我國公告第347573號半導體封裝構造擴散 膠之示意圖； 第4圖：另一習用美國專利第5,331，2〇5號半導體封裝（ 構造之示意圖； 第5圖：本發明第一較佳實施例半導體封裝構造之上視 第6圖：本發明第5圖沿6_6線剖面圖。 第7圖：：發：第二較佳實施例半導趙封裝構造之上視 第8圊：本發明第7圖沿8_8線剖面圖 12 導線 圖號說明： 1〇 基板 402795 五、發明說明（5^ 13 膠 21 第 二 封 膠 體 22 晶 片 墊 24 導 線 25 導 線 架 31 晶 片 32 導 線 34 封 膠 體 41 晶 片 42 導 線 44 第 二 固 定 部 45 封 膠 體 20 第—封膠體 23 晶片 3〇 基板 3 3 固定部 4 0 基板 4 3 第一固定部 實施例說明 清再參照第五及六圖所示，本發明第一較佳實施例主要 包含·'基板30、一晶片31、數條導線32及一固定部33。該 基板30之上表面上置該晶片32，該數條導線32則連接該基 板30上表面之數個焊墊〔未標示〕及該晶片31上表面之數 個焊塾〔未標示〕。該固定部33係由低熱膨脹係數之環邊、 樹，物質形成，而該固定部33位於基板3〇之上表面且環繞 於晶片31之周緣並包覆數條導線32之主要部份，該數條導 線32之主要部份則位於導線32之中段，該導線32中段因衝 線而容易產生導線之間接觸，因此，分別連接於基板30上 表面之數個焊墊及晶片31上表面之數個焊墊之該導線32兩 端仍未被該固定部33覆蓋。此外，該固定部33未覆蓋晶片 31之上表面，因此，該固定部33只與部份基板3〇上表面形 成界面，而因該固定部33材料用量減少使該固定部33硬化 時間亦減少。當該固定部33硬化時，再將封膠灌入晶片31 上形成一封膠體34。 4027915—4027 V. Description of the invention (4) --- Part is not covered on the wafer 'to avoid the strain caused by different expansion coefficients from acting on the wafer. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention and the accompanying drawings in detail as follows. Figure 1: Schematic diagram of the conventional semiconductor package structure of China's public announcement No. 3475 73 without glue spraying; Figure 2: Schematic diagram of the conventional semiconductor package structure of China's public notice No. 347573 for glue dispensing; Figure 3: Conventional Chinese public notice No. 347573 Schematic diagram of semiconductor packaging structure diffusion glue; Figure 4: Another conventional US Pat. No. 5,331,205 semiconductor package (Schematic diagram of the structure; Figure 5: Top view of the semiconductor package structure of the first preferred embodiment of the present invention Fig. 6: Sectional view taken along line 6-6 of Fig. 5 of the present invention. Fig. 7: Hair: Top view of the semiconducting Zhao package structure of the second preferred embodiment. Fig. 8: Sectional view taken along line 8_8 of Fig. 7 of the present invention. Wire drawing number description: 10 substrate 402795 V. Description of the invention (5 ^ 13 glue 21 second sealant 22 wafer pad 24 wire 25 lead frame 31 chip 32 wire 34 sealant 41 chip 42 wire 44 second fixing part 45 sealant 20 第 — 胶 胶 23 Wafer 30. Substrate 3 3 Fixing part 4 0 Substrate 4 3 Example of the first fixing part. Refer to Figures 5 and 6 again. The first preferred embodiment of the invention mainly includes a substrate 30, a wafer 31, a plurality of wires 32, and a fixing portion 33. The wafer 32 is placed on the upper surface of the substrate 30, and the plurality of wires 32 are connected to the substrate 30 Several pads [not labeled] on the upper surface and several pads [not labeled] on the upper surface of the wafer 31. The fixing portion 33 is formed of a ring edge, a tree, and a material having a low thermal expansion coefficient, and the fixing portion 33 It is located on the upper surface of the substrate 30 and surrounds the periphery of the wafer 31 and covers the main part of the plurality of wires 32. The main part of the plurality of wires 32 is located in the middle section of the wire 32. Contacts between the leads are apt to occur. Therefore, both ends of the lead 32 connected to the pads on the upper surface of the substrate 30 and the pads on the upper surface of the wafer 31 are not covered by the fixing portion 33. In addition, the fixing The portion 33 does not cover the upper surface of the wafer 31. Therefore, the fixing portion 33 only forms an interface with the upper surface of a part of the substrate 30, and the curing time of the fixing portion 33 is also reduced due to the reduction in the amount of material used in the fixing portion 33. When the portion 33 is hardened, the sealing compound is poured into the wafer 31 A colloid 34 is formed on it. 4027915

請再參照第一、四及五圖所示’本發明之固定部33較我 國專利公告第3475 73號之膠13及較美國專利第5, 33丨，2〇5 破之第一封膠體20所使用材料減少’而本發明之固定部33 所需硬化時間較膠1 3及第一封膠體2 0所需硬化時間減少， 且本發明仍可保護導線3 2避免產生衝線。此外，本發明之 晶片31較我國專利公告第34 7573號之晶片11及較美國專利 第5, 331，205號之晶片23，該晶片31未被固定部33覆蓋， 而避免在晶片31散熱時，由晶片31、固定部33及封膠體〔 未標示〕之不同膨脹係數所造成的應變力作用於該晶片3丄 上0 請再參照第七及八圖所示，本發明第二較佳實施例主要 包含一基板40、一晶片41、數條導線42、一第一固定部43 及一第二固定部44。該基板40之上表面上置該晶片42，該 數條導線42則連接該基板40上表面之數個焊墊〔未標示〕< — 及該晶片41上表面之數個焊墊〔未標示〕。該第一固定部 . 43及第二固定部44分別位於該基板40上表面及晶片41之周 圍附近’其中該第一固定部43包覆最容易造成導線衝線之 注膠口 〔未標示〕附近之數條導線42，而該第二固定部44 包覆次容易造成導線衝線之注膠口相對角落附近之數條導 線42，另有一部份數條導線42則未被第一固定部43或第二 固定部44包覆’該未被包覆之數條導線42在灌膠時所受的 封膠衝力較小。該第一固定部43及第二固定部44包覆該數 條導線42之主要部份，該數條導線42之主要部份則位於導 線42之中段，因此’分別連接於基板4〇上表面之數個焊塾Please refer to the first, fourth and fifth illustrations again. 'The fixing part 33 of the present invention is less than the glue 13 of China Patent Publication No. 3475 73 and the first seal colloid 20 which is more broken than that of US Patent No. 5, 33 丨, 205. The material used is reduced, and the curing time required for the fixing portion 33 of the present invention is shorter than that required for the glue 13 and the first sealing compound 20, and the present invention can still protect the wire 32 from being punched. In addition, the wafer 31 of the present invention is better than the wafer 11 of Chinese Patent Publication No. 34 7573 and the wafer 23 of US Patent No. 5, 331, 205. The wafer 31 is not covered by the fixing portion 33 to avoid the heat dissipation of the wafer 31 The strain force caused by the different expansion coefficients of the wafer 31, the fixing portion 33, and the sealing compound [not marked] acts on the wafer 3 丄 0. Please refer to the seventh and eighth figures again, the second preferred implementation of the present invention The example mainly includes a substrate 40, a wafer 41, a plurality of wires 42, a first fixing portion 43 and a second fixing portion 44. The wafer 42 is placed on the upper surface of the substrate 40, and the plurality of wires 42 are connected to several pads on the upper surface of the substrate 40 [not labeled] < and several pads on the upper surface of the wafer 41 [not labeled 〕. The first fixing portion 43 and the second fixing portion 44 are respectively located near the upper surface of the substrate 40 and the periphery of the wafer 41. Among them, the first fixing portion 43 covers the glue injection port (not labeled) that is most likely to cause the lead to punch. Nearby wires 42, and the second fixing portion 44 covers the wires 42 near the opposite corner of the injection port of the wires, and another portion of the wires 42 is not covered by the first fixing portion 43 or the second fixing portion 44 is coated with the uncoated wires 42 and the encapsulation impulse received by the conductive wires 42 is relatively small. The first fixing portion 43 and the second fixing portion 44 cover the main portion of the plurality of wires 42, and the main portion of the plurality of wires 42 are located in the middle portion of the wire 42, and thus are 'connected to the upper surface of the substrate 40 respectively. Welding pads

第9頁 402795 五、發明說明（7) 及晶片41上表面之數個焊墊之該數條導線42兩端仍未被該 第一固定部4 3及第二固定部44覆蓋。此外，該第一固定部 43及第二固定部44未覆蓋晶片41之上表面，因此，該第一 固定部43及第二固定部44只與部份基板40上表面形成界面 。當該第一固定部43及第二固定部44硬化時，再將封膝灌 入晶片41上形成一封膠體45。 請再參照第一、四及七圖所示，本發明之第一固定部43 及第二固定部44較我國專利公告第347573號之膠13及較美 國專利第5, 331，205號之第一封膠體20所使用材料減少， 而本發明之第一固定部4 3及第二固定部44所需硬化時間較： 膠13及第一封膠體20所需硬化時間減少’且本發明仍可保 護導線32避免產生衝線。此外，本發明之晶片41較我國專 利公告第347573號之晶片11及較美國專利第5, 33.1，205號 之晶片23，該晶片41未被第一固定部43及第二固定部44, 蓋，而避免在晶片41散熱時，由晶片41、第一固定部43^ , 第二固定部44及封膠體〔未標示〕之不同膨脹係數所造成 的應變力作用於該晶片41上。 請再參照第五及七圖所示，本發明之防止晶片引線偏移 之半導體裝置製法，其係在基板30、40表面上晶片31、41 邊緣之數個導線區分別形成一固定部33或第一固定部43及 第一固定部44，再等該固定部33或第一固定部43及第一固 定部44硬化形成一絕緣分隔固定體，該固定部33或第一固 定部43及第一固定部44硬化後在該晶片31、41及導線32、 42上注入封膠形成一封膠體34、45。Page 9 402795 V. Description of the invention (7) and both ends of the plurality of wires 42 of the plurality of pads on the upper surface of the wafer 41 are not covered by the first fixing portion 43 and the second fixing portion 44. In addition, the first fixing portion 43 and the second fixing portion 44 do not cover the upper surface of the wafer 41. Therefore, the first fixing portion 43 and the second fixing portion 44 form an interface with only the upper surface of the substrate 40. When the first fixing portion 43 and the second fixing portion 44 are hardened, the knee seal is poured into the wafer 41 to form a gel 45. Please refer to the first, fourth, and seventh figures again. The first fixing portion 43 and the second fixing portion 44 of the present invention are better than the glue 13 of China Patent Bulletin No. 347573 and the No. 5 of US Patent No. 5,331,205. The material used for one colloid 20 is reduced, and the hardening time required for the first fixing part 43 and the second fixing part 44 of the present invention is less than: The hardening time required for the glue 13 and the first sealing colloid 20 is reduced, and the present invention can still The protective wire 32 is protected from a punch line. In addition, the wafer 41 of the present invention is higher than the wafer 11 of Chinese Patent Publication No. 347573 and the wafer 23 of US Patent No. 5, 33.1, 205, and the wafer 41 is not covered by the first fixing portion 43 and the second fixing portion 44. While avoiding the heat dissipation of the wafer 41, the strain force caused by the different expansion coefficients of the wafer 41, the first fixing portion 43 ^, the second fixing portion 44 and the sealing compound [not labeled] acts on the wafer 41. Please refer to FIG. 5 and FIG. 7 again. The semiconductor device manufacturing method for preventing chip lead offset according to the present invention is to form a fixed portion 33 or a plurality of lead areas on the surfaces of the substrates 30 and 40 on the edges of the wafers 31 and 41 respectively The first fixing portion 43 and the first fixing portion 44, and after the fixing portion 33 or the first fixing portion 43 and the first fixing portion 44 are hardened to form an insulating partition fixing body, the fixing portion 33 or the first fixing portion 43 and the first fixing portion After a fixing portion 44 is hardened, a sealant is injected on the wafers 31 and 41 and the wires 32 and 42 to form a glue body 34 and 45.

第10頁 402795Page 10 402795

Claims (1)

1. 一種防止晶片引線偏移之半導體裝置，其包含 一基板，其包含一上表面； 晶片’其位於該基板上表面上； 而另一端則連 複數條導線其一端連接該基板之上表面 接該晶片之上表面；及 一第一固定部’其只包覆位於該基板上表面注膠口附 之導線，其中該第一固定部只包覆導線之中段，而使 之兩端未被該第一固定部覆蓋。 、 2. 依申請專利範圍第1項所述之防止晶片引線偏移之半導 體裝置’其另包含一第二固定部位於該第一固定部及注踢 口之相對位置上’其中該第二固定部只包覆位於該第一固 定部及注膠口之相對位置上之導線’並且該第二固定部只 包覆該數條導線之中段’使該數條導線之兩端未被該 固定部覆蓋。 3. 依申請專利範圍第1項或第2項所述之防止晶片引線偏移 之半導體裝置，其中該固定部係以低熱膨脹係數材料形 成。 4. 依申請專利範圍第1項或第2項所述之防止晶片引線偏移 之半導體裝置，其中該固定部係由環氧樹脂形成。1. A semiconductor device for preventing a chip lead from shifting, comprising a substrate including an upper surface; the chip is located on the upper surface of the substrate; and the other end is connected with a plurality of wires, and one end is connected to the upper surface of the substrate. The upper surface of the wafer; and a first fixing portion 'which only covers the wires attached to the glue injection port on the upper surface of the substrate, wherein the first fixing portion only covers the middle portion of the wires so that both ends are not The first fixing portion is covered. 2. The semiconductor device for preventing chip lead offset according to item 1 of the scope of the patent application, which further includes a second fixing portion located at a relative position between the first fixing portion and the injection-kick opening, wherein the second fixing portion Part only covers the wires located at the relative positions of the first fixing part and the injection port, and the second fixing part only covers the middle section of the plurality of wires, so that both ends of the plurality of wires are not fixed by the fixing part cover. 3. The semiconductor device for preventing chip lead offset according to item 1 or item 2 of the scope of the patent application, wherein the fixing portion is formed of a material with a low thermal expansion coefficient. 4. The semiconductor device for preventing chip lead displacement according to item 1 or item 2 of the scope of patent application, wherein the fixing portion is formed of epoxy resin. 5. —種防止晶片引線偏移之半導體裝置製法，其包含下列5. A method for manufacturing a semiconductor device for preventing chip lead offset, which includes the following POO-075.ptc 第13頁POO-075.ptc Page 13 裝置，其包含： 一種防止晶片引線偏移之半導趙 一基板’其包含一上表面； ~晶片，其位於該基板上表面上 數條導線，其一端連接該基板之 接該晶片之上表面；及 上表面而另一端則連 一固定部，其位於該基板之上表 緣； 面並位於該晶片之邊 其中一部份該數條導線被該固定部覆蓋。 一種防止晶片引線偏移之半導體裝置，其包含： —基板，其包含一上表面； —晶片，其位於該基板上表面上； 數條導線，其一端連接該基板之上表面而另一端則連 接該晶片之上表面；及 第一固定部，其位於該基板上表面之注勝 位於該晶片之邊緣； 其中一部份該數條導線被該第一固定部覆蓋 、依申請專利範圍第2項所述之防止晶片引線 導.體裝置，其中另包含一第二固定部，該第 口附近並A device comprising: a semi-conductor Zhao Yi substrate which prevents a wafer lead from shifting, which includes an upper surface; a wafer, which is located on the upper surface of the substrate, a plurality of wires, and one end of which is connected to the substrate and the upper surface of the wafer; And the upper surface and the other end is connected with a fixing portion, which is located on the surface edge of the substrate; a portion of the plurality of wires is covered by the fixing portion on the surface and on the edge of the wafer. A semiconductor device for preventing a chip lead from shifting, comprising:-a substrate including an upper surface;-a wafer located on the upper surface of the substrate; a plurality of wires having one end connected to the upper surface of the substrate and the other end connected The upper surface of the wafer; and a first fixing portion, the note located on the upper surface of the substrate is located on the edge of the wafer; a part of the plurality of wires is covered by the first fixing portion, according to item 2 of the scope of patent application The device for preventing a lead of a chip from being guided further includes a second fixing portion, and the vicinity of the mouth is 偏移之半 二固定部 位於該第一固定部及注膠口相對位置上。 、依申請專利範圍第1項所述之防止晶片引線偏移之半 導體裝置，其中該固定部環繞於該晶片周緣並包覆該 數條導線。 、依申請專利範圍第1、2、3或4項所述之防止晶片引線 偏移之半導體裝置，其中該固定部只包覆該數條導線 40^795 六、申請專利範圍 之中段，使該數條導線之兩端未被該固定部覆蓋。 6、依申請專利範圍第5項所述之防止晶片引線偏移之半 導體裝置，其中該固定部係以低熱膨脹係數材料形成 7、 依申請專利範圍第5項所述之防止晶片引線偏移之半 導體裝置’其中該固定部係由環氧樹脂形成。 8、 依申請專利範圍第1項所述之防止晶片引線偏移之半 導體裝置，其中該晶片未被該固定部覆蓋。 9、 一種防止晶片引線偏移之半導體裝置製法，其包含下 列步驟： a. 在一基板表面上晶片邊緣之數個導線區分別形成一固 定部； b. 等該固定部硬化形成一絕緣分隔固定體；及 c. 該固定部硬化後在該晶片及數個導線上注入封 一封膠體。 料利範圍第9項所述之防止晶片引線偏移< 導趙裝置製法，其中該固定部只覆蓋數個導線之中= 引線偏移之半 口附近。 引線偏移之半 ’該數個固定 11、依申請專利範圍第9項所述之防止晶片 導趙裝置製法，其中該固定部位於注膠 1 2、依申請專利範圍第9項所述之防止晶片 導體裝置製法’其中另包含數個固定部 部分別位於該晶片周緣。The offset half of the second fixing portion is located at the relative position between the first fixing portion and the injection port. 2. The semiconductor device for preventing chip lead displacement according to item 1 of the scope of the patent application, wherein the fixing portion surrounds the periphery of the chip and covers the plurality of wires. 2. According to the semiconductor device for preventing chip lead offset according to item 1, 2, 3 or 4 of the scope of patent application, wherein the fixed portion only covers the several wires 40 ^ 795 6. The middle section of the scope of patent application Both ends of the plurality of wires are not covered by the fixing portion. 6. The semiconductor device for preventing chip lead offset according to item 5 of the scope of the patent application, wherein the fixing portion is formed of a material with a low thermal expansion coefficient 7. The device for preventing chip lead offset according to item 5 of the scope of the patent application In the semiconductor device, the fixing portion is formed of epoxy resin. 8. The semiconductor device for preventing a chip lead from shifting according to item 1 of the scope of the patent application, wherein the chip is not covered by the fixing portion. 9. A method for manufacturing a semiconductor device for preventing a chip lead from shifting, comprising the following steps: a. Forming a fixing portion on each of a plurality of lead areas on a substrate surface of the wafer edge; b. Waiting for the fixing portion to harden to form an insulation separation fixing Body; and c. After the fixing part is hardened, a piece of gel is injected and sealed on the wafer and several wires. The method for preventing chip lead offset described in item 9 of the material benefit range < Zhao Zhao device manufacturing method, wherein the fixed portion covers only a few of the leads = near the half of the lead offset. Half of the lead offset 'The number of fixings 11. According to the method of preventing wafer guide device described in item 9 of the scope of the patent application, the fixing part is located at the injection 1 2. The prevention is based on the item 9 of the scope of patent application The method for manufacturing a wafer conductor device further includes a plurality of fixing portions respectively located at the periphery of the wafer. 1. 一種防止晶片引線偏移之半導體裝置，其包含 一基板，其包含一上表面； 晶片’其位於該基板上表面上； 而另一端則連 複數條導線其一端連接該基板之上表面 接該晶片之上表面；及 一第一固定部’其只包覆位於該基板上表面注膠口附 之導線，其中該第一固定部只包覆導線之中段，而使 之兩端未被該第一固定部覆蓋。 、 2. 依申請專利範圍第1項所述之防止晶片引線偏移之半導 體裝置’其另包含一第二固定部位於該第一固定部及注踢 口之相對位置上’其中該第二固定部只包覆位於該第一固 定部及注膠口之相對位置上之導線’並且該第二固定部只 包覆該數條導線之中段’使該數條導線之兩端未被該 固定部覆蓋。 3. 依申請專利範圍第1項或第2項所述之防止晶片引線偏移 之半導體裝置，其中該固定部係以低熱膨脹係數材料形 成。 4. 依申請專利範圍第1項或第2項所述之防止晶片引線偏移 之半導體裝置，其中該固定部係由環氧樹脂形成。1. A semiconductor device for preventing a chip lead from shifting, comprising a substrate including an upper surface; the chip is located on the upper surface of the substrate; and the other end is connected with a plurality of wires, and one end is connected to the upper surface of the substrate. The upper surface of the wafer; and a first fixing portion 'which only covers the wires attached to the glue injection port on the upper surface of the substrate, wherein the first fixing portion only covers the middle portion of the wires so that both ends are not The first fixing portion is covered. 2. The semiconductor device for preventing chip lead offset according to item 1 of the scope of the patent application, which further includes a second fixing portion located at a relative position between the first fixing portion and the injection-kick opening, wherein the second fixing portion Part only covers the wires located at the relative positions of the first fixing part and the injection port, and the second fixing part only covers the middle section of the plurality of wires, so that both ends of the plurality of wires are not fixed by the fixing part cover. 3. The semiconductor device for preventing chip lead offset according to item 1 or item 2 of the scope of the patent application, wherein the fixing portion is formed of a material with a low thermal expansion coefficient. 4. The semiconductor device for preventing chip lead displacement according to item 1 or item 2 of the scope of patent application, wherein the fixing portion is formed of epoxy resin. 5. —種防止晶片引線偏移之半導體裝置製法，其包含下列5. A method for manufacturing a semiconductor device for preventing chip lead offset, which includes the following POO-075.ptc 第13頁POO-075.ptc Page 13 步驟： 提供一晶片設於一基板上表面； 將複數條導線之一端連接於該基板之上表面，另一端則 連接於該晶片之上表面； 該 未 固 形成第一固定部於該基板上表面之注膠口附近，其中 第一固定部只包覆位於該基板上表面注膠口附近之導線 並且該第一固定部只包覆導線之中段，而使導線之兩端 被該第一固定部覆蓋；及 一在該第一固定部硬化後，形成一封膠體覆蓋於該第一 定部、晶片、導線以及基板上表面之一部份上。 6.依申請專利範圍第5項所述之防止晶片引線偏移之半導 體裝置製法’其另包含形成一第二固定部於該第一固定部 及注膠口之相對位置上，其中該第二固定部只包覆位 第一固定部及注膠口之相對位置上之導線，並且該第 定部只包覆導線之中段，而使導線之兩端未被該第二 部覆蓋。 & 7.，申請專利範圍第5項或第6項所述之防止晶片引線偏移 之半導體裝置製法，其中該固定部係以低熱膨脹係數材 形成。 寸 8.依申請專利範圍第5項或第6項所述之防止晶片引線偏 之半導體裝置製法，其中該固定部係由環氧樹脂形成。Steps: Provide a chip on the upper surface of a substrate; connect one end of the plurality of wires to the upper surface of the substrate, and connect the other end to the upper surface of the wafer; the unfixed first fixing portion is formed on the upper surface of the substrate Near the glue injection port, wherein the first fixing part only covers the wire near the glue injection port on the upper surface of the substrate and the first fixing part only covers the middle section of the wire, so that both ends of the wire are covered by the first fixing part Covering; and after the first fixing portion is hardened, a gel is formed to cover the first fixing portion, the chip, the wires, and a portion of the upper surface of the substrate. 6. According to the method of manufacturing a semiconductor device for preventing chip lead displacement according to item 5 of the scope of the patent application, it further includes forming a second fixing portion on the relative position of the first fixing portion and the injection port, wherein the second The fixed part only covers the wires at the relative positions of the first fixed part and the injection port, and the first fixed part only covers the middle section of the wire, so that both ends of the wire are not covered by the second part. & 7. The method of manufacturing a semiconductor device for preventing a wafer lead from shifting as described in claim 5 or 6, wherein the fixing portion is formed of a low coefficient of thermal expansion material. 8. The method for manufacturing a semiconductor device according to claim 5 or 6 of the scope of patent application, wherein the fixing portion is formed of epoxy resin. P00-075.ptcP00-075.ptc 第14頁Page 14
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