TW495890B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- TW495890B TW495890B TW090114063A TW90114063A TW495890B TW 495890 B TW495890 B TW 495890B TW 090114063 A TW090114063 A TW 090114063A TW 90114063 A TW90114063 A TW 90114063A TW 495890 B TW495890 B TW 495890B
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- semiconductor device
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- metal layer
- semiconductor wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
495890495890
【發明領域】 本發明係有關於一種半導體裝置及其製造方法，尤關 於一種散熱速率快，且厚度薄的半導體裝置及其製造方 法0 【習知技術】 隨著積體電路高度集積化，及消費市場的需求，半導 體封裝體係越趨於輕薄短小，並已發展出許多類型之封裝 型態。例如，QFN (Quad Flat No-Lead)、QFP(Quad Flat[Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device with a fast heat dissipation rate and a thin thickness and a method for manufacturing the same. [Known Technology] As integrated circuits are highly integrated, and As the consumer market demands, semiconductor packaging systems are becoming thinner, lighter and shorter, and many types of packaging types have been developed. For example, QFN (Quad Flat No-Lead), QFP (Quad Flat
Package)等封裝形式的半導體裝置。 如圖1為習知QFN(Quad Flat No-Lead)半導體裝置1， 其主要包括一半導體晶片11、複數條導電線丨2、一導線架 1 3、及一封膠體1 5。Package) and other semiconductor devices. As shown in FIG. 1, a conventional QFN (Quad Flat No-Lead) semiconductor device 1 mainly includes a semiconductor wafer 11, a plurality of conductive wires 2, a lead frame 1 3, and a colloid 15.
其中，導線架13包括複數根引腳（lead) 131、及晶片 承座（die pad)132。該半導體晶片11係以銀膠（silver paste)、環氧樹脂（epoxy resin)、或其他黏著劑16而黏 著固定於該晶片承座1 32上，且該半導體晶片1 j係利用複 數條導電線1 2例如金線（g〇 1 d w i r e )分別與引腳1 3 1電連 接。該封膠體1 5係將該半導體晶片1丨、該等導電線丨2、及 導線架1 3包覆。一般，封膠體1 5係以塑料（mo 1 d i ng compound)例如熱固性塑膠所構成。 於習知的QFN封裝製程中，導線架丨3的一面係粘著膠 〒14，以防止封膠製程（molding process)中產生溢膜/ (flash)現象，避免導致半導體裝置！安裝於印刷電路^反上The lead frame 13 includes a plurality of leads 131 and a die pad 132. The semiconductor wafer 11 is adhered and fixed to the wafer holder 1 32 with silver paste, epoxy resin, or other adhesives 16, and the semiconductor wafer 1 j is formed by using a plurality of conductive wires. 1 2 For example, a gold wire (g0 1 dwire) is electrically connected to the pins 1 3 1 respectively. The sealing compound 15 covers the semiconductor wafer 1 丨, the conductive wires 2, and the lead frame 13. Generally, the sealing compound 15 is made of a plastic (mo 1 d i ng compound) such as a thermosetting plastic. In the conventional QFN packaging process, one side of the lead frame 丨 3 is adhered with adhesive 〒14 to prevent the flash film / (flash) phenomenon during the molding process and avoid causing semiconductor devices! Mounted on printed circuit board
五、發明說明（2) 時導電性能不良。 ㈣=?文！體裝置1而，，由於其半導體晶片11係必 ^猎由黏者劑16固定於該晶片承座132，因此 除去’其半導體裝置1之整體厚度係ΐ “、、法有效減低。此外，就該種半導體裝置丨而十， 半導體晶片1 1外露之一面並未有特殊處理（:全/、 =因^就半導體裝置1整體而言，其散熱效果並不是很 更It Α如：使半導體裝置更薄、散熱速率更快、且 成本更低貝為一重要的課題。 【發明概 鑑於 薄、散熱 為達 括一半導 體。其中 具有 漏 要】 上述的 速率快 上述目 體晶片 ，半導 空區域 ;封膠 有該層 與導線架 線，且鍍 體之外。 本發明亦提 步驟·提供一具 線架；經導線架 片粘著於膠帶上 課題，本發明之目的在於提供一種厚度 、且成本低之半導體裝置及其製造方法。 的，本發明係提供一種半導體裝置，其包 、一導線架、複數條導電線、及一封^匕 體晶片之一面係鑛有一今屬思·、苦 • ★ 4屬層，導線架係 ，禝數條導電線係用以電連接 體係包覆半導體晶片、導線架+ 曰片 金屬之半導體晶片的一面係露出於該封膠 供-種半導體裝置製造方法，其包括下列 有漏空區域，且其一面粘著有一膠帶之導 之漏空區域而將一鍍有金屬層的半導體晶 ;以複數條導電線將該半導體晶片與該^ ^yjQyy) ----- 五、發明說明（3) 線架電連接； 電線 一面露出。 藉由本發 帶來黏著固定 的厚度，且膠 導體裝置的厚 此外，Μ 半導體晶^ 並露出於封膠 再者，藉 半導體裝置係 導線架，藉以 attach)製程： 以一封膠體包覆半導體晶片、導線架、及導 除去膠帶，以使該半導體晶片鍍有金屬層的 於藉著膠 環氧樹脂 可減少半 〇 法，由於 金屬層， 熱速率。 法，由於 有膠帶之 晶（d i e 明之半導體裝置及其製造方法，由 半導體晶片，故可省去晶片承座及 帶係於封膠製程完成後去除，故更 度’且增加半導體裝置的散熱速率 由本發明之半導體裝置及其製造方 一面係鍍有熱導係數高如金（Au)之 體之外，故可增加半導體裝置的散 由本發明之半導體裝置及其製造方 採用具有漏空區域，且其一面粘著 省去以環氧樹脂或其他黏著劑之黏 故可降低半導體裝置的成本。 【較佳實施例之詳細說明】 =下將參考相關圖式，來說明本發明較佳實施例之半 ，體波，。在具體說明本發明之較佳實施例前欲先說明的 =R ί說明上之便利’|實施例中之圖號係、大部份沿用上 迷圖號。 圖2Α、2Β所示係為一QFN型之半導體晶片封裝構迕， =該圖所示，本發明之較佳實施例的半導體裝置丨，之導線 架13係具有一漏空區域（〇peni )，言^ ^ ^ ^ 該導線㈣之中央部，亦即，該導線架13係去=片成:座V. Description of the invention (2) Poor electrical conductivity. ㈣ =? Text! Since the semiconductor device 11 must be fixed to the wafer holder 132 by the adhesive 16, the overall thickness of the semiconductor device 1 is effectively reduced. In addition, This kind of semiconductor device 丨 And ten, the exposed surface of the semiconductor wafer 1 1 is not specially treated (: all /, = because the overall heat dissipation effect of the semiconductor device 1 is not very much). Thinner, faster heat dissipation rate, and lower cost is an important subject. [Invention of the invention is thin, heat dissipation is a semiconductor. There are omissions] The above rate is faster than the above-mentioned body wafer, semi-conducting empty area The sealant has this layer and the wire frame, and it is other than the plated body. The invention also mentions the steps of providing a wire frame; the problem of sticking to the tape through the wire frame sheet; the purpose of the present invention is to provide a thickness and cost Low semiconductor device and manufacturing method thereof. The present invention provides a semiconductor device including a package, a lead frame, a plurality of conductive wires, and a surface of a dagger body wafer.思 · 、 苦 • ★ 4 genus layers, lead frame system, several conductive wires are used to electrically connect the system to cover the semiconductor wafer, one side of the semiconductor frame of the lead frame + metal is exposed to the sealant. A method for manufacturing a semiconductor device, which includes the following vacant regions, and a side of a vacant region with an adhesive tape adhered on one side thereof is a semiconductor crystal plated with a metal layer; the semiconductor wafer is connected to the semiconductor wafer with a plurality of conductive wires. yjQyy) ----- V. Description of the invention (3) The wire frame is electrically connected; one side of the wire is exposed. The thickness of the adhesive is fixed by the hair band, and the thickness of the rubber conductor device is thick. In addition, the M semiconductor crystal is exposed to the sealant. In addition, the semiconductor device is a lead frame, so as to attach). The semiconductor wafer, lead frame, and conductive tape are covered with a piece of gel, so that the semiconductor wafer is plated with a metal layer. The method of reducing by half is due to the metal layer and the heat rate. Because of the semiconductor device with a tape (die semiconductor device and its manufacturing method), which uses semiconductor wafers, the wafer holder and belt system can be omitted. It is removed after the sealing process is completed, so the heat dissipation rate of the semiconductor device is increased, and the semiconductor device and its manufacturing side are coated with a body having a high thermal conductivity such as gold (Au), so the semiconductor device can be increased. The semiconductor device of the present invention and the manufacturer thereof have a vacant region, and one side of the semiconductor device can be reduced by using epoxy resin or other adhesives to reduce the cost of the semiconductor device. [Detailed description of the preferred embodiment ] = The following will describe the half of the preferred embodiment of the present invention, body waves, with reference to the related drawings. = R To facilitate the description of the preferred embodiment of the present invention = R ‚convenience in description '| Example The figure numbers in the figure are mostly the same as those in the previous figure. Figures 2A and 2B show a QFN-type semiconductor chip package structure. = This figure shows a semiconductor device according to a preferred embodiment of the present invention 丨The lead frame 13 has an empty area (〇peni), that is, the central part of the lead frame ，, that is, the lead frame 13 is connected to a piece of:
第6頁 ^5890 五、發明說明（4) _____ 2的邛分，只留下引腳1 31形 、、 、 面枯著有膠帶14。 σ刀，並且，導線架13的 半體晶片1 1係經由此導加 固定於膠帶14上，據以取代木13之漏空區域將其粘著 此外，於本實施例中代；；晶程序。 -金屬層111。此金屬層U1係二：巧11的-面係鍍有 所構成。言亥半導體晶片"藉;係數尚之金屬例如金 數條導電線12例如金線，將^ Γ 4者固定後，再以複 該封膠體15係包覆半導體t、，數根引腳131電連接。 架13。其中，封膠體15材可：11 :導電線12、及導線 塑料。 J為熱固性塑膠或其他絕緣的 封膠製程完畢後，便可丰^ w^ 11 ^ ^ ^ Μ 1 1 Λ 去除膝並使半導體晶片 丄丄锻有金屬層111的一面露出。 如圖3所示，半導體盤署1，， -垂妗…從 表置1 為本發明較佳實施例的第 樣’於本實施例中，除晶片承座132的部分以 均與圖2的半導體裝置r相同。於本實施例中， ^線木13以触刻的方式去除晶片承座132中承載半導體晶 的區域，但保留晶片承座丨32週邊的接地部丨33，以供 連接如金線的接地線1 2，，進而達接地功能。 如圖4所示，其為本發明較佳實施例的第三實施態 樣0 本實施例的半導體裝置2係一種QFp(Quad Flat Package)型之半導體晶片封裝構造。 於本實施例中，導線架2 6包括外引腳（ou t er 495890 五、發明說明（5) l』ad)261 ’及内引腳（inner· lead) 262。外弓丨腳如 =接至外部電路，而内引腳262係以數條的 +導體晶片21電連接。本實施例中’當半導體裝置2正^ 時，晶片21係位於該半導體裝置2的下方虛 ' ' 置 ° it 匕夕卜，<ji 於打線接合（wire bonding)，該導線架26夕〜⑴、 呈彎折狀，據以形成如圖所示的低置區，俾腳262係 …與半導體晶片21的相對高度。 俾^短内引腳 又’本實施例亦同於前述利用具有办 =著有膠帶之導線架，將一面鑛有例如=導二 至屬層211的半導體晶片21，經由該導 ^導係^數阿 枯著固宗A微册μ 拉朴 木之漏工區域而 牛=固疋於^上。接者’進行前述之打線 -面露出。於本實施例中，ί =體; 之導電線11、封膠體15相同。 ,體25係與月,J述 以下將說明本發明半導體裝置製造方法。 如圖5所示，本發明之丰逡 31中，提供-具有漏空區域=置:二方法先於步驟 線架。接著，在步驟32中者有一膠帶之導 -面鑛有如金的金屬層的半； = 之漏空區域而將 接著，在步驟33中，進丄 =二片枯者固定於膠帶上。 亦即以如厶硷从、# 仃打線接合（wire bonding)程序， 接。接著電線將半導體晶片與導線架進行電連 ^ 得者，在步驟34 Φ，、备， 半導辦曰U ^ Α 中 途仃封膠程序，以一封膠體包覆 去豚‘，以佶：1木、及導電線。最後，在步驟35中，除 ^以使5亥半導體晶片錢有金屬層的-面露出。Page 6 ^ 5890 V. Description of the invention (4) _____ 2 points, leaving only pins 1 31 shaped, tapered, and taped. σ knife, and the half-body wafer 11 of the lead frame 13 is fixed to the adhesive tape 14 through this guide, thereby replacing the empty area of the wood 13 and adhering it. In addition, it is replaced in this embodiment; . -Metal layer 111. This metal layer U1 is composed of two: the eleven-side system is plated with. Yanhai semiconductor wafer " Borrowing a metal with a high coefficient such as gold, several conductive wires 12 such as gold wires, after fixing ^ Γ 4 and then covering the semiconductor t with the sealing compound 15 series, several pins 131 are electrically connection.架 13。 Frame 13. Among them, the sealing material 15 can be: 11: conductive wire 12, and lead plastic. J is a thermosetting plastic or other insulating sealing compound. After the manufacturing process is completed, it can be removed ^ w ^ 11 ^ ^ ^ 1 1 Λ to remove the knee and expose the side of the semiconductor wafer upset forged with the metal layer 111. As shown in FIG. 3, the semiconductor disk arrangement 1, and the vertical axis 1 is the first embodiment of the preferred embodiment of the present invention. In this embodiment, the parts except the wafer holder 132 are the same as those in FIG. 2. The semiconductor devices r are the same. In this embodiment, the wire wood 13 removes the region carrying the semiconductor crystals in the wafer holder 132 in a engraved manner, but retains the grounding portion 33 around the wafer holder 丨 32 for connecting a ground wire such as a gold wire. 1 2, and then to ground function. As shown in FIG. 4, it is a third embodiment of the preferred embodiment of the present invention. 0 The semiconductor device 2 of this embodiment is a QFp (Quad Flat Package) type semiconductor wafer package structure. In this embodiment, the lead frame 26 includes an outer pin (outer 495890 V. Description of the invention (5) l "ad) 261 'and an inner lead 262. The outer bow and feet are connected to an external circuit, and the inner pin 262 is electrically connected by a plurality of + conductor chips 21. In the present embodiment, 'when the semiconductor device 2 is positive, the chip 21 is located below the semiconductor device 2', and it is placed at the position where it is wire bonding, and the lead frame 26 is (2) It is bent to form a low-positioned area as shown in the figure, and the feet 262 are relative to the height of the semiconductor wafer 21.俾 ^ The short inner pin is also the same as the previous embodiment using a lead frame with an adhesive tape and a semiconductor wafer 21 on one side with, for example, a lead to a metal layer 211. The number of dead spots in Guzong A micro-book μ Lapumu missed work area and cattle = 疋 疋 on ^. The receiver 'performs the aforementioned threading-the surface is exposed. In the present embodiment, the conductive wire 11 and the sealing compound 15 are the same. The body 25 series and the month are described below. The method for manufacturing the semiconductor device of the present invention will be described below. As shown in FIG. 5, in the present invention, in the present invention, the method of providing-having a vacant region = setting: two methods precedes the step of the wire frame. Next, in step 32, there is a tape guide-the surface of the metal layer is like half of the metal layer of gold; = the vacant area and will be next. Then, in step 33, the two pieces of dead are fixed on the tape. That is, wire bonding (wire bonding) procedures such as 厶 硷 from and 厶 硷 are used to connect. Then, the wire electrically connects the semiconductor wafer with the lead frame. ^ The winner, in step 34 Φ, 备, semi-conductor, U ^ Α midway through the sealing process, cover with a piece of gel to remove the dolphin, with 佶: 1 Wooden and conductive wires. Finally, in step 35, ^ is divided to expose the -side of the 5H semiconductor wafer with a metal layer.
第8頁Page 8
ΙΗΙι 五、發明說明（6) 每上所述，由认立， -膠帶之導線架漏 晶程序令製程成太名去使用環衣往成本。此外，由於 體晶片，故可省去曰H ; ’方日日片承座及環 於封膠製程後去除，故更可使半 者，由於半導體晶片中鍍有如金 封膠體之外，故可使散熱的速率 於本實施例之詳細說明中所 了易於說明本發明之技術内容， 制於該實施例，在不超出本發明 圍之情況，可作種種變化實施。 空區域 氣樹脂 藉著膠 氧樹脂 導體裝 的金屬 增加。 提出之 而並非 之精神 ’且其一 或其他黏 帶來黏著 的厚度， 置的厚度 層的一面 具體的實 將本發明 及以下申 面粘著有 著劑於黏 固定半導 又，膠帶 降低。再 係露出於 施例僅為 狹義地限 請專利範 _ΙΗΙι 5. Description of the invention (6) As mentioned above, from the standpoint,-the lead frame leakage process of the tape makes the process too expensive to use the ring coat to the cost. In addition, because of the body wafer, H can be omitted; 'Fangri and Japan film holders and rings are removed after the sealing process, so it can be half, because the semiconductor wafer is plated with gold sealant, so it can The rate of heat dissipation is described in the detailed description of this embodiment to easily explain the technical content of the present invention. Based on this embodiment, various changes can be implemented without exceeding the scope of the present invention. Empty area The amount of metal in the air-filled resin via conductive resin is increased. The proposed rather than the spirit 'and one or other of the adhesives bring the thickness of the adhesive, and the thickness of one layer of the layer is concretely adhered to the present invention and the following applications with an adhesive to fix the semiconductor, and the tape is reduced. It is exposed in the examples only in a narrow sense.
495890 圖式簡單說明 【圖式之簡單說明】 圖1為一示意圖，顯示習知QFN型的半導體裝置。 圖2A、2B為一示意圖，顯示本發明較佳實施例的半導 體裝置，其中，圖2B係表示本發明較佳實施例之半導體裝 置除去膠帶後的示意圖。 圖3為一示意圖，顯示本發明較佳實施例的半導體裝 置第二實施態樣。 圖4為一示意圖，顯示本發明較佳實施例的半導體裝 置第三實施態樣。 圖5為一流程圖，顯示本發明較佳實施例的半導體裝 置製造方法。 【圖式符號說明】 1 半導體裝置 1， 半導體裝置 1，， 半導體裝置 11 半導體晶片 111 金屬層 12， 接地線 12 導電線 13 導線架 131 引腳 132 晶片承座 133 接地部495890 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a schematic diagram showing a conventional QFN type semiconductor device. 2A and 2B are schematic views showing a semiconductor device according to a preferred embodiment of the present invention, wherein FIG. 2B is a schematic view showing a semiconductor device according to a preferred embodiment of the present invention after the tape is removed. FIG. 3 is a schematic diagram showing a second embodiment of a semiconductor device according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram showing a third embodiment of a semiconductor device according to a preferred embodiment of the present invention. FIG. 5 is a flowchart showing a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. [Illustration of Symbols] 1 semiconductor device 1, semiconductor device 1, semiconductor device 11 semiconductor wafer 111 metal layer 12, ground wire 12 conductive wire 13 lead frame 131 pins 132 wafer holder 133 grounding portion
第10頁 495890 圖式簡單說明 14 膠 帶 15 封 膠 體 16 黏 著 劑 2 半 導 體 裝 置 21 半 導 體 晶 片 211 金 屬 層 22 導 電 線 25 封 膠 體 26 導 線 架 261 外 引 腳 262 内 引 腳 31 提 供 ^ — 具 有 漏 空 區 域 ，且 其一 面枯 著 有 膠 帶之導線 架 32 將 一 鍍 有 金 屬 層 的 半 導體 晶片 粘著 於 膠 帶 上 33 打 線 接 合 34 封 膠 35 除 去 膠 帶Page 10 495890 Brief description of the drawings 14 Tape 15 Sealant 16 Adhesive 2 Semiconductor device 21 Semiconductor wafer 211 Metal layer 22 Conductive wire 25 Sealant 26 Lead frame 261 Outer pin 262 Inner pin 31 Provided ^ — with a void area And one side is covered with a lead frame with adhesive tape 32 Adhering a metal-plated semiconductor wafer to the adhesive tape 33 Wire bonding 34 Sealant 35 Removing the adhesive tape
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090114063A TW495890B (en) | 2001-06-11 | 2001-06-11 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090114063A TW495890B (en) | 2001-06-11 | 2001-06-11 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW495890B true TW495890B (en) | 2002-07-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| TW090114063A TW495890B (en) | 2001-06-11 | 2001-06-11 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW495890B (en) |
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2001
- 2001-06-11 TW TW090114063A patent/TW495890B/en not_active IP Right Cessation
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