TW432646B - Manufacturing method for semiconductor chip packaging structure with no outer leads - Google Patents

Manufacturing method for semiconductor chip packaging structure with no outer leads Download PDF

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Publication number
TW432646B
TW432646B TW088117027A TW88117027A TW432646B TW 432646 B TW432646 B TW 432646B TW 088117027 A TW088117027 A TW 088117027A TW 88117027 A TW88117027 A TW 88117027A TW 432646 B TW432646 B TW 432646B
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TW
Taiwan
Prior art keywords
lead frame
mold
lead
wafer
manufacturing
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TW088117027A
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Chinese (zh)
Inventor
Chun-Chi Lee
Su Tao
Chun-Hung Lin
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Advanced Semiconductor Eng
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Priority to TW088117027A priority Critical patent/TW432646B/en
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Publication of TW432646B publication Critical patent/TW432646B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

A manufacturing method for semiconductor chip packaging structure with no outer leads which includes the following steps: fixing a semiconductor chip on the die of a lead frame in which the lead frame comprises a plurality of wires configured at the periphery of the die and each wire comprises a recess configured at the position to be punched; electrically connecting the inner ends of the plurality of leads to the semiconductor chip; attaching a thin film on the lower mold of a mold; clamping the mold so that the semiconductor chip is located in the cavity on the upper mold of the mold, and the lead frame is located on the thin film; injecting the encapsulation resin into the cavity; curing the encapsulation resin; opening the mold to take out the molded part; and, slicing the molded part so that the slicing lines are corresponding to the recess of the plurality of leads and making the singulation process easier and more precise. In the lead frame according to the present invention, the lower surface of each lead is smaller than the upper surface so that it has a tapered side profile which can coordinate with the thin film to effectively prevent the flash occurrence.

Description

P43264 6 五、發明說明（1) 發明領域· 本發明係有關於一種電子裝置，特別有關於一種半導 體晶片封裝構造以及其製造方法，其中該半導體晶片係為 一封膠體包覆並且該半導體晶片之下表面係裸露於該封膠 體。 先前技術： 第一圊係為一習用半導體晶片封裝構造，其包含一導 線架（lead frame)用以承载一晶片1〇(^該導線架包含複 數條導線具有外腳部（outer leads portion)106以及内腳 部1 0 7。該晶片1 0 0係藉銀膠1 1 4黏著固定於一晶片承座1 1 1 —其係以數個支撐肋條（未示於圖中）連接於該導線架。 該導線架之外腳部1 0 6係用以電性連接至一外部電路。該 晶片1 0 0具有複數個晶片銲墊11 7利用複數條連接線 (bonding wire)115電性連接該導線架之内腳部107。該晶 片100、晶片承座111、導線架之内腳部107、以及複數條 連接線1 1 5係包覆於一封膠體1 1 6。該封膠體1 1 6係以絕緣 材料例如環氧樹脂（epoxy )製成。 由於該封膠體11 6係完全環繞該晶片1 0 0，所以該晶片 1 0 0正常運作所產生的熱必須完全經由該封膠體1 1 6傳出’ 而由於該封膠體1 1 6的絕緣特性，使得該晶片1 〇 〇的散熱會 受到阻礙，因此，在某些狀況下，其將在該習用半導通晶 片封裝構造内產生高溫而可能損傷或損壞該晶片1〇0 ° 因此半導體業界發展出無外引腳半導體封裝構造 2〇〇(參照第二圖），其大致包含一晶片210承載於一導線架P43264 6 V. Description of the Invention (1) Field of the Invention The present invention relates to an electronic device, and in particular to a semiconductor wafer package structure and a method for manufacturing the same, wherein the semiconductor wafer is a colloidal envelope and the semiconductor wafer is The lower surface is exposed to the sealant. Prior technology: The first line is a conventional semiconductor chip package structure, which includes a lead frame for carrying a chip 10 (the lead frame includes a plurality of wires with outer leads portion 106) And the inner leg 1 0. The chip 1 0 0 is fixed to a chip holder 1 1 1 by silver glue 1 1 4-it is connected to the lead frame with several supporting ribs (not shown in the figure). The outer legs 10 of the lead frame are used to electrically connect to an external circuit. The chip 100 has a plurality of chip pads 11 7 and the wires are electrically connected by a plurality of bonding wires 115 The inner leg 107 of the frame. The wafer 100, the wafer holder 111, the inner leg 107 of the lead frame, and a plurality of connecting wires 1 1 5 are covered with a gel 1 1 6. The gel 1 1 6 Made of insulating material such as epoxy. Since the sealing compound 116 completely surrounds the chip 100, the heat generated by the normal operation of the chip 100 must be completely transmitted through the sealing compound 1 1 6出 'And due to the insulating properties of the sealing compound 1 16, the heat dissipation of the wafer 100 will be Obstructed, therefore, under certain conditions, it will generate high temperature in the conventional semi-conducting wafer package structure, which may damage or damage the wafer 100 °. Therefore, the semiconductor industry has developed an outer leadless semiconductor package structure 200. (Refer to the second figure), which generally includes a chip 210 carried on a lead frame

第5頁 五、發明説明（2) 之晶片承座220 °該導線架包含複數條導線2 30藉由複數條 金線240電性連接至該晶片2 1 0。該晶片以及導線架係包覆 於一封膠體250 ’使得該導線架之下表面係裸露於該封膠 體，因此該半導體晶片正常運作所產生的熱可直接經由該 導線架之晶片承座220傳出’因而可增進該無外引腳半導 體封裝構造200之散熱效率。然而因為該導線架之下表面 係裸露於該封膠體’因此在該複數條導線2 3 0以及晶片承 座220之邊緣220a、230a容易產生溢膠（flash)而影響其銲 錫連接可靠性（solder joint reliability)。 發明概要· 本發明之主要目的係提供一種無外引腳半導體晶片封 裝構造之方法1其在封膠製程中利用一薄膜來防止溢膠的 產生。 本發明之次要目的係提供一種無外引腳半導體晶片封 裝構造之方法，其在封膠製程中利用一上而下漸細 (tapered)之導線架配合一薄膜而有效防止溢膠的產生。 本發明之另一目的係提供一種無外引腳半導體晶片封 裝構造之方法，其利用一在預定被裁切之位置 (to-be-punched position)設有凹陷之導線架，使單一化 製程（singulation process)更輕易、準綠。 根據本發明較佳實施例之製造無外引腳半導體晶片封 裝構造之方法，其包含下列步驟：（A) 將一半導體晶片固 定於一導線架之晶片承座上’該半導體晶片具有複數個晶 片銲墊，其中該導線架包含複數條導線設於該晶片承座之Page 5 5. Description of the invention (2) Wafer holder 220 ° The lead frame contains a plurality of wires 2 30 and is electrically connected to the wafer 2 1 0 by a plurality of gold wires 240. The chip and the lead frame are covered with a piece of gel 250 ′ so that the lower surface of the lead frame is exposed to the sealing gel, so the heat generated by the normal operation of the semiconductor wafer can be directly transmitted through the chip holder 220 of the lead frame. Therefore, the heat dissipation efficiency of the outer-lead-free semiconductor package structure 200 can be improved. However, because the lower surface of the lead frame is exposed to the sealing compound, flashes are easily generated on the plurality of wires 230 and the edges 220a and 230a of the chip holder 220, which affects the solder connection reliability. joint reliability). SUMMARY OF THE INVENTION The main object of the present invention is to provide a method 1 for packaging a semiconductor wafer package without outer pins. The method uses a thin film to prevent the occurrence of glue overflow during the sealing process. A secondary object of the present invention is to provide a method for packaging a semiconductor wafer with no outer pins, which utilizes a tapered lead frame with a thin film during the sealing process to effectively prevent the occurrence of glue overflow. Another object of the present invention is to provide a method for packaging a non-lead semiconductor chip package, which utilizes a lead frame provided with a recess at a predetermined to-be-punched position to simplify the manufacturing process ( singulation process) is easier and quasi-green. A method for manufacturing an outer-lead-free semiconductor wafer package structure according to a preferred embodiment of the present invention includes the following steps: (A) fixing a semiconductor wafer to a wafer holder of a lead frame; the semiconductor wafer has a plurality of wafers; A solder pad, wherein the lead frame includes a plurality of leads disposed on the wafer holder

第6頁 i432646 五、發明說明（3) 週邊’並且該每一條導線係具有一凹陷設於預定被裁切之 位置；（B)將複數條連接線分別連接該導線架之複數條導 線之内端以及該半導體晶片之複數個晶片鲜墊；（C)將一 薄膜吸附於一模具之下模，該模具之上模具有一模穴； (D)將該模具密合夾緊使得該半導體晶片係位於該模穴中 並且該導線架係位於該薄膜上；（E )將封膠塑料注入該模 穴中；（F )硬化該封踢塑料；（G)打開該鑄模以取出該模 製品；及（Η )裁切該模製品使得其裁切線係對應於該複數 條導線之凹陷。根據本發明之導線架，其每一條導線之下 表面係小於其上表面，因而具有一由上而下漸細 (t a p e r e d )之側邊輪廓。 根據本發明之無外引腳半導體晶片封裝構造之方法， 其在封膠製程中’將待封膠之半導體晶片及導線架置於一 吸附於下模具之薄膜上’由於該薄膜係以耐熱且具彈性之 材質製成，因此提供良好之密封效果而可防止溢膠產生在 該無外引腳半導體晶片封裝構造之下表面，從而確保其銲 錫連接可靠性（solder joint reliability)。此外由於根 據本發明之導線架，其每一條導線具有一由上而下漸細 (tapered)之侧邊輪廓’因而可使薄膜產生更好之密封效 果而有效防止溢膠的產生。 根據本發明之導線架，由於其在預定裁切位置設有凹 陷，使得該模製品可以沿該導線架之凹陷裁切，而使單一 化製程（singulation process)更輕易、準確。 圖示說明：Page 6 i432646 V. Description of the invention (3) Peripheral 'and each of the conductors has a recess provided at a position to be cut; (B) Connect a plurality of connecting wires to the plurality of wires of the lead frame respectively And a plurality of wafer pads of the semiconductor wafer; (C) a film is adsorbed on a mold under the mold, the mold has a cavity on the mold; (D) the mold is tightly clamped so that the semiconductor wafer system Located in the cavity and the lead frame is located on the film; (E) injecting a sealing plastic into the cavity; (F) hardening the sealing plastic; (G) opening the mold to take out the molded product; and (Ii) Cutting the molded product so that its cutting line corresponds to the depression of the plurality of wires. According to the lead frame of the present invention, the lower surface of each wire is smaller than the upper surface thereof, and therefore has a side profile that tapers from top to bottom (t a p e r e d). According to the method for packaging a non-lead semiconductor chip package according to the present invention, during the sealing process, the semiconductor wafer and the lead frame to be sealed are placed on a film adsorbed to a lower mold because the film is heat-resistant and It is made of elastic material, so it provides a good sealing effect and prevents overflow from occurring on the lower surface of the outer-lead-free semiconductor chip package structure, thereby ensuring solder joint reliability. In addition, since each lead wire according to the present invention has a tapered side profile 'from top to bottom, the film can have a better sealing effect and effectively prevent the occurrence of glue overflow. According to the lead frame of the present invention, since the recess is provided at a predetermined cutting position, the molded product can be cut along the recess of the lead frame, thereby making the singulation process easier and more accurate. Graphic description:

第 ^^^^1 頁Page ^^^^ 1

i5 ^326 4 6 五、發明說明（4) 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯特徵，下文特舉本發明較佳實施例，並配合所附圖 示，作詳細說明如下。 第1圖：習用半導體晶片封裝構造之剖面圖； 第2圖：另一習用半導體晶片封裝構造之剖面圖； 第3圖：根據本發明之用以製造無外引腳半導體晶片 封裝構造之一導線架之上視圖；及 第4圖至第7圖：其揭示一種根據本發明較佳實施利 之製 造無外引 丨腳半 導體晶片 封 裝 構 造之 方法。 圖號 說明： 100 晶 片 106 外 腳 部 107 内 腳 部 111 晶 片 承 座 1 14 銀 膠 115 連 接 線 116 封 膠 體 1 17 晶 片 銲 墊 200 無 外 引 腳半導體封裝: 構造 2 10 晶 片 220 晶 片 承 座 230 導 線 240 金 線 250 封 膠 體 220a 邊 緣 2 3 0 a 邊 緣 300 單 元 305 晶 片 承 座 307 支 撐 肋條 3 0 7 a 凹 陷 310 導 線 310a 凹 陷 320 半 導 體 晶片 3 2 0 a 晶 片 銲 墊 322 銀 膠 324 金 線 330 薄 膜 340 下 模 342 上 模 342a 模 穴 350 塑 料 線 360 裁 切 線 發明 說明：i5 ^ 326 4 6 V. Description of the invention (4) In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention in detail with the accompanying drawings for details. described as follows. Figure 1: A cross-sectional view of a conventional semiconductor chip package structure; Figure 2: A cross-sectional view of another conventional semiconductor chip package structure; Figure 3: A lead wire for manufacturing a non-leadless semiconductor chip package structure according to the present invention Top view of the rack; and Figures 4 to 7: it discloses a method for manufacturing a non-leadless semiconductor chip package structure according to a preferred embodiment of the present invention. Description of drawing number: 100 chip 106 outer leg 107 inner leg 111 chip holder 1 14 silver glue 115 connecting wire 116 sealing compound 1 17 chip pad 200 semiconductor package without outer lead: structure 2 10 chip 220 chip holder 230 Conductor 240 Gold wire 250 Sealant 220a Edge 2 3 0 a Edge 300 Unit 305 Wafer holder 307 Support rib 3 0 7 a Recess 310 Wire 310a Recess 320 Semiconductor wafer 3 2 0 a Wafer pad 322 Silver glue 324 Gold wire 330 Film 340 lower mold 342 upper mold 342a cavity 350 plastic line 360 cutting line invention description:

第8頁 κ<ψ： 五、發明說明（5) 第三圖係為根據本發明之用以製造無外引腳半導體晶 片封裝構造之一導線架，其包含複數個單元，其大致被標 示為300。該導線架之每一單元300大致包含一晶片承座 305以及複數條導線310設於該晶片承座305之週邊。該晶 片承座305係藉由支撐肋條307連接至該導線架，其中該晶 片承座305之下表面較佳係小於其上表面使其具有一由上 而下漸細（t ap e r e d )之側邊輪廓。該導線架每一條導線3 1 0 之下表面係小於其上表面，因而具有一由上而下漸細 (tapered)之側邊輪廓，且該每一條導線310係具有一凹陷 310a設於其預定被裁切之位置（參見第四圖）。較佳地， 該每一個支撐肋條307之下表面係小於其上表面，並且該 每一個支撐助條307係具有一凹陷307a設於其預定被裁切 之位置。 根據本發明之導線架，其係由一薄金屬條，經由蝕刻 或衝壓而形成一類似於第三圖所示之圖案（pattern)。該 導線架較佳係由銅或其合金製成。此外該導線架亦可由 鐵、錄或其合金製成，然後艘上一層銅。該凹陷310a、 3〇7a較佳係以蝕刻或衝壓形成於該導線310及支撐肋條307 之下表面。 第五圖至第七圖揭示一種製造根據本發明之半導體晶 片封裝構造之方法。 請參照第五圖，一半導體晶片320藉由一導電膠例如銀 膠322固著於該導線架之晶片承座305上》該半導體晶片 320具有複數個晶片銲墊320a設在其上表面，用以連接其Page 8 κ < ψ: V. Description of the invention (5) The third diagram is a lead frame for manufacturing an outer-lead-free semiconductor chip packaging structure according to the present invention, which includes a plurality of cells, which are roughly labeled as 300. Each unit 300 of the lead frame generally includes a wafer holder 305 and a plurality of wires 310 disposed on the periphery of the wafer holder 305. The wafer holder 305 is connected to the lead frame by supporting ribs 307. The lower surface of the wafer holder 305 is preferably smaller than the upper surface so that it has a tapered side from top to bottom. Edge contour. The lower surface of each of the wires 3 1 0 of the lead frame is smaller than the upper surface thereof, and thus has a tapered side profile from top to bottom, and each of the wires 310 has a recess 310 a provided at a predetermined position. Where it was cut (see figure 4). Preferably, the lower surface of each of the supporting ribs 307 is smaller than the upper surface thereof, and each of the supporting ribs 307 has a recess 307a provided at a position where it is to be cut. The lead frame according to the present invention is formed from a thin metal strip by etching or stamping to form a pattern similar to that shown in the third figure. The lead frame is preferably made of copper or an alloy thereof. In addition, the lead frame can also be made of iron, iron or its alloy, and then be coated with copper. The depressions 310 a and 307 a are preferably formed on the lower surface of the conductive wire 310 and the supporting rib 307 by etching or stamping. 5 to 7 illustrate a method of manufacturing a semiconductor wafer package structure according to the present invention. Referring to the fifth figure, a semiconductor wafer 320 is fixed on a wafer holder 305 of the lead frame by a conductive paste such as silver paste 322. The semiconductor wafer 320 has a plurality of wafer pads 320a provided on the upper surface thereof. To connect it

第9頁 1 二 !/ 五、發明說明（6) 内部電路。該複數條連接線例如金線324係利用習知的線 鋒（wire bonding)技術分別連接該導線31Q之内端以及相 對應之晶片銲墊3 20a。 請參照第六圖，一薄膜330被吸附於一模具之下模 340。該薄膜330係先覆蓋於該下模340之表面，然後將空 氣經由複數個通孔以一抽氣機構（a i r s u c k i n g mechanism)(未示於圖中）吸走而將該薄膜330固定於該 模具之下模340上。該模具之上模342具有一模穴3 42 a其大 致符合該無外引腳半導體晶片封裝構造之外形。該薄膜 3 3 0較佳係以耐熱且具彈性之材質製成，例如鐵氟龍 (Teflon (polytetrafluroethylene， PTFE))或乙稀四氟 乙稀（ethylene tetrafluroethylene， ETFE)。 請參照第七圖，將該模具密合夾緊使得該半導體晶片 320係位於該模穴342a中並且該導線架係位於該薄膜330 上"然後，將封膠塑料注入該模穴342a中，在該封膠塑料 硬化後，打開該鑄模並且取出該模製品。 最後，將該模製品上多餘之封膠材料去除，並且進行 單一化製程（singulation process)，即沿該導線架上之 凹陷3 0 7a、31 0a裁切該而模製品得到根據本發明之最終產 物。 請再參照第三圖，塑料線（c 〇 m ρ 〇 u n d 1 i n e ) 3 5 0係表示 形成在該導線架上之封膠體之邊界。而該進行「去鑄澆 道」製程後之模製產品，係沿裁切線（p u n c h i n g 1 i n e ) 3 6 0 切割成個別單元，而製得該半導體封裝構造之最終成品。Page 9 1 II! / V. Description of the invention (6) Internal circuit. The plurality of connecting wires, such as gold wire 324, are connected to the inner end of the wire 31Q and the corresponding wafer pad 3 20a by using a conventional wire bonding technology, respectively. Referring to the sixth figure, a thin film 330 is attracted to a lower mold 340. The film 330 is first covered on the surface of the lower mold 340, and then the air is sucked away through an air sucking mechanism (not shown) through a plurality of through holes to fix the film 330 to the mold. The lower mold 340 is on. The upper mold 342 of the mold has a cavity 3 42 a which substantially conforms to the outer shape of the outer-lead-free semiconductor chip package structure. The film 3 3 0 is preferably made of a heat-resistant and elastic material, such as Teflon (polytetrafluroethylene (PTFE)) or ethylene tetrafluroethylene (ETFE). Referring to the seventh figure, the mold is tightly clamped so that the semiconductor wafer 320 is located in the cavity 342a and the lead frame is located on the film 330 " Then, a sealing plastic is injected into the cavity 342a, After the sealant has hardened, the mold is opened and the molded product is removed. Finally, the excess sealant material on the molding is removed and a singulation process is performed, that is, cutting along the depressions 3 7a, 3 0a on the lead frame, and the molding is finally obtained according to the present invention. product. Please refer to the third figure again. The plastic wire (c 0 m ρ 0 u n d 1 ine) 3 50 represents the boundary of the sealing compound formed on the lead frame. The molded product after the "de-casting runner" process is cut into individual units along a cutting line (p u n c h i n g 1 i n e) 3 60 to obtain a final product of the semiconductor package structure.

P432646___ 五、發明說明（7) 根據本發明之無外引腳半導體晶片封裝構造，其係可 以類似於其他無外引腳裝置（leadless device)之方式安 裝於一基板’例如一印刷電路板。該印刷電路板可先以錫 膏網版印刷（screen print)成對應於該晶片封裝構造底部 之導線圖案（p a 11 e r η )。然後將該封裝構造對正置於該印 刷電路板上加以回銲即可。可以理解的是，該封裝構造底 部所暴露之導線亦可先印上錫膏（solder paste)，再安裝 至基板。 請再參照第四圊以及第七圖，當該模具密合夾緊時， 該導線架係被壓迫而陷入具彈性之薄膜3 3 0上，因此提供 良好之密封效果而防止溢膠產生在該無外引腳半導體晶片 封裝構造之下表面’從而確保其銲錫連接可靠性（s〇lder joint re 1 i abi 1 i ty) »此外根據本發明之導線架，由於其 每一條導線具有一由上而下漸細（tapered)之側邊輪廓， 因而可使該每一條導線更易陷入該薄膜3 3 〇，而增加該每 一條導線突出於該封裝構造底部之高度（stand-〇ff)，而 該導線凸出部（lead protrusion)係可增進可煤性 (sol derab i1i t y)。 根據本發明之導線架’由於其在預定裁切位置設有ΰϊ 陷’使得該模製品可以沿該導線架之凹陷裁切，而使單一 化製程（singulation process)更輕易、準綠。 雖然本發明已以前述較佳實饱例揭示，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍内’當可作各種之更動與修改，因此本發明之保護P432646___ 5. Description of the invention (7) The outer-lead-free semiconductor chip package structure according to the present invention can be mounted on a substrate 'such as a printed circuit board in a manner similar to other leadless devices. The printed circuit board may first be screen printed with a solder paste to form a wire pattern (p a 11 e r η) corresponding to the bottom of the chip package structure. The package structure is then placed on the printed circuit board and re-soldered. It can be understood that the wires exposed at the bottom of the package structure can also be printed with a solder paste before being mounted on the substrate. Please refer to the fourth figure and the seventh figure again. When the mold is tightly clamped, the lead frame is pressed into the elastic film 3 3 0, so it provides a good sealing effect and prevents the overflow of glue. The lower surface of the outer-lead-free semiconductor chip package structure, thereby ensuring solder joint reliability (solder joint re 1 i abi 1 i ty) »In addition, according to the lead frame of the present invention, The tapered side profile is lower, so that each wire can be more easily trapped in the film 3 3 0, and the height (stand-off) of each wire protruding from the bottom of the package structure is increased, and the Lead protrusions can improve the coal solabability (sol derab i1i ty). The lead frame according to the present invention is provided with a depression at a predetermined cutting position, so that the molded product can be cut along the depression of the lead frame, thereby making the singulation process easier and quasi-green. Although the present invention has been disclosed with the foregoing preferred examples, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Invention protection

辦4 326 4 6 , 五、發明說明（8) 範圍當視後附之申請專利範圍所界定者為準。 第12頁Office 4 326 4 6, V. Description of the invention (8) The scope shall be determined by the scope of the attached patent application. Page 12

Claims (1)

-4 326 4 6 六、申請專利範圍 1 、一種製造無外引腳半導體晶片封裝構造之方法，其包 含下列步驟： 提供一導線架，其包含一晶月承座以及複數條導線設 於該晶片承座之週邊，該每一條導線係具有一凹陷設於其 預定被裁切之位置； 固定一半導體晶片於該導線架之晶片承座上，該半導 體晶片具有複數個晶片銲墊； 將複數條連接線分別連接該複數條導線之内端以及該 半導體晶片之複數個晶片銲墊； 提供一模具，其包含一上模以及一下模，該上模具有 一模穴； 提供一薄膜吸附於該下模； 密合夾緊該模具使得該半導體晶片係位於該模穴中並 且該導線架係位於該薄膜上； 將封膠塑料注入該模穴中； 硬化該封膠塑料； 打開該鑄模以取出該模製品；及 裁切該模製品使得其裁切線係對應於該複數條導線之 凹陷。 2 、依申請專利範圍第1項之製造無外引腳半導體晶片封 裝構造之方法，其中該薄膜係以耐熱且具彈性之材質製 成。-4 326 4 6 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor chip package structure with no leads, including the following steps: Provide a lead frame including a crystal moon socket and a plurality of wires provided on the chip Around the pedestal, each of the conductors has a recess provided at a position where it is to be cut; a semiconductor wafer is fixed on the wafer holder of the lead frame, the semiconductor wafer has a plurality of wafer pads; The connecting wire connects the inner ends of the plurality of wires and the plurality of wafer pads of the semiconductor wafer, respectively. A mold is provided, which includes an upper mold and a lower mold, and the upper mold has a cavity; a film is adsorbed on the lower mold. ; Tightly clamping the mold so that the semiconductor wafer is located in the cavity and the lead frame is located on the film; injecting an encapsulant into the cavity; hardening the encapsulant; opening the mold to remove the mold An article; and cutting the molded article such that its cutting line corresponds to the depression of the plurality of wires. 2. The method for manufacturing an outer-lead-free semiconductor wafer packaging structure according to item 1 of the scope of patent application, wherein the film is made of a heat-resistant and elastic material. 第13頁 E4 32 6 4 6 ： 六、申請專利範圍 3 、依申請專利範圍第1項之製造無外引腳半導體晶片封 裝構造之方法，其中該導線架之每一條導線之下表面係小. 於其上表面。 4 、依申請專利範圍第1項之製造無外引腳半導體晶>1封 裝構造之方法，其中該導線架包含複數個支撐肋條用以連 接該晶>!承座，該每一個支撐肋條之下表面係小於其上表 面，並且該每一個支撐肋條係具有一凹陷設於其預定被裁 切之位置。 5 、依申請專利範圍第1項之製造無外引腳半導體晶片封 裝構造之方法，其中該導線架之晶片承座之下表面係小於 其上表面。 6 、一種用以製造無外引腳半導體晶片封裝構造之導線 架，其包含一晶片承座以及複數條導線設於該晶承座之 週邊，其中每一條導線係具有一凹陷設於其預定被裁切之 位置。 7 、依申請專利範圍第6項之用以製造無外引腳半導體晶 片封裝構造之導線架，其中該導線架之每一條導線之下表 面係小於其上表面。 8 、依申請專利範圍第6項之用以製造無外引腳半導體晶Page 13 E4 32 6 4 6: VI. Patent Application Range 3, The method for manufacturing a non-lead semiconductor chip package structure according to item 1 of the patent application range, wherein the lower surface of each wire of the lead frame is small. On its upper surface. 4. A method for manufacturing an outer-lead-free semiconductor crystal according to item 1 of the scope of the patent application> 1 package structure, wherein the lead frame includes a plurality of support ribs for connecting the crystal >! socket, each of the support ribs The lower surface is smaller than the upper surface, and each of the support ribs has a recess provided at a position where it is to be cut. 5. The method for manufacturing an outer-lead-free semiconductor wafer packaging structure according to item 1 of the scope of the patent application, wherein the lower surface of the wafer holder of the lead frame is smaller than the upper surface thereof. 6. A lead frame for manufacturing an outer-lead-free semiconductor chip package structure, comprising a wafer socket and a plurality of wires provided on the periphery of the wafer socket, wherein each of the wires has a recess provided in a predetermined place thereof. Crop position. 7. A lead frame for manufacturing a semiconductor chip package structure with no outer pins according to item 6 of the scope of the patent application, wherein the lower surface of each lead of the lead frame is smaller than its upper surface. 8. Manufacture of non-lead semiconductor crystals according to item 6 of the scope of patent application 第丨4頁 > P4 3 2 6 4 6 六、申請專利範圍 片封裝構造之導線架，其卡該導線架包含複數個支撐肋條 用以連接該晶片承座，該每一個支撐肋條之下表面係小於 其上表面，並且該每一個支撐肋條係具有一凹陷設於其預 定被裁切之位置。Page 丨 4 > P4 3 2 6 4 6 6. The lead frame of the patent application chip package structure, the lead frame includes a plurality of support ribs for connecting the wafer holder, and the lower surface of each support rib The system is smaller than its upper surface, and each of the support ribs has a recess provided at a position where it is intended to be cut. 第15頁Page 15
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