JP2005093635A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device Download PDF

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JP2005093635A
JP2005093635A JP2003323986A JP2003323986A JP2005093635A JP 2005093635 A JP2005093635 A JP 2005093635A JP 2003323986 A JP2003323986 A JP 2003323986A JP 2003323986 A JP2003323986 A JP 2003323986A JP 2005093635 A JP2005093635 A JP 2005093635A
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resin
semiconductor chip
lead frame
circuit board
semiconductor device
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Masashi Hoya
昌志 保谷
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in a product by preventing resin from flowing to an adjacent region for mounting a circuit board and from overlapping with a resin adhesive layer on the substrate, when coating a semiconductor chip mounted to a lead frame with a protective resin. <P>SOLUTION: In a resin-sealed semiconductor device, circuit boards 3 in which a semiconductor chip 2 and a circuit component 4 are packaged on the upper surface of the lead frame 1 are mounted side by side, and the periphery is sealed by a mold resin 6. In a configuration, where the semiconductor chip is mounted to the frame by solder 7, then the semiconductor chip is coated with the protective region 9, and then the circuit board is joined to the frame by the resin adhesive 8; a protruding line part (dam part) 1a is formed along the boundary between a region for mounting the semiconductor chip and a region for mounting an insulating substrate on the upper surface of the lead frame, thus preventing the protective region 9 applied to the semiconductor chip and the periphery from being shielded by the protruding line part, flowing to the region for mounting the circuit board, and overlapping with the resin adhesive 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、混成集積回路等を対象とした樹脂封止型半導体装置、詳しくはそのパッケージ構造に関する。   The present invention relates to a resin-encapsulated semiconductor device intended for a hybrid integrated circuit or the like, and more particularly to its package structure.

まず、本発明の実施対象となる頭記半導体装置の従来構造を図３に示す。図において、１はリードフレーム（銅材）、２はリードフレーム１の上面に搭載したパワー半導体チップ（ベアチップ）、３は制御用ＩＣなどの回路部品４を実装し、半導体チップ２に並置してリードフレーム１に搭載した回路基板（セラミックなどの厚膜絶縁基板）、５は半導体チップ３，回路部品４，およびリードフレーム１のインナーリードとの相互間に配線したアルミワイヤ、６は周域全体を封止したモールド樹脂（例えばエポキシ樹脂）である。   First, FIG. 3 shows a conventional structure of a head semiconductor device to be implemented by the present invention. In the figure, 1 is a lead frame (copper material), 2 is a power semiconductor chip (bare chip) mounted on the upper surface of the lead frame 1, and 3 is mounted with a circuit component 4 such as a control IC and juxtaposed with the semiconductor chip 2. Circuit board (thick film insulating substrate such as ceramic) mounted on the lead frame 1, 5 is an aluminum wire wired between the semiconductor chip 3, the circuit component 4 and the inner lead of the lead frame 1, and 6 is the entire circumference Is a mold resin (for example, epoxy resin).

ここで、半導体チップ２は半田７を導電接合材としてリードフレーム１に半田マウントし、回路基板３はシリコーン樹脂などの樹脂接着剤８を用いてリードフレーム１の上面に固着しており、さらに半導体チップ３の上面およびその周域には、モールド樹脂６との密着性強化，および熱応力緩和を目的に耐熱性の高いポリイミド樹脂などの保護樹脂９をコーティングしている。   Here, the semiconductor chip 2 is solder-mounted on the lead frame 1 using the solder 7 as a conductive bonding material, and the circuit board 3 is fixed to the upper surface of the lead frame 1 using a resin adhesive 8 such as silicone resin. The upper surface of the chip 3 and the peripheral area thereof are coated with a protective resin 9 such as a polyimide resin having high heat resistance for the purpose of enhancing adhesion with the mold resin 6 and relaxing thermal stress.

一方、前記と同様にリードフレームにパワー半導体チップ，および制御用ＩＣなどを実装した回路基板を搭載してその周域をモールド樹脂で封止したマルチチップパワーデバイスの樹脂封止型半導体装置について、半導体チップ２を被覆した前記の樹脂保護層９とは別に、回路基板３および回路部品４に保護樹脂層をコーティングするとともに、この保護樹脂層をさらに半導体チップ２の領域まで拡大して半導体チップ２を二重の保護樹脂層で覆うようにして、リードフレーム１に接合した半導体チップ２の半田接合層にクラックが発生するのを防ぐようにした構成のものが知られている（例えば、特許文献１参照）。
特開平１０−２０９３４４号公報 On the other hand, for a resin-encapsulated semiconductor device of a multi-chip power device in which a circuit board on which a power semiconductor chip and a control IC are mounted on a lead frame is mounted in the same manner as described above, and its peripheral area is sealed with a mold resin. In addition to the resin protective layer 9 covering the semiconductor chip 2, the circuit board 3 and the circuit component 4 are coated with a protective resin layer, and the protective resin layer is further expanded to the area of the semiconductor chip 2. Is known to be covered with a double protective resin layer to prevent cracks from occurring in the solder joint layer of the semiconductor chip 2 joined to the lead frame 1 (for example, Patent Documents). 1).
JP-A-10-209344

ところで、図３に示した従来構造では次記のような問題点がある。すなわち、リードフレーム１の上面は平坦面で、かつ半導体チップ２と回路基板３とは近接してリードフレーム１の上面に配置されていことから、半導体チップ２に保護樹脂層（ポリイミド樹脂）９をコーティングする際にその樹脂が流動して周囲に広がり、図４で示すように回路基板３をリードフレーム１に接合している樹脂接着剤（シリコーン樹脂）８の一部に重なり合うようになることがある。   Incidentally, the conventional structure shown in FIG. 3 has the following problems. That is, since the upper surface of the lead frame 1 is a flat surface and the semiconductor chip 2 and the circuit board 3 are disposed close to each other on the upper surface of the lead frame 1, a protective resin layer (polyimide resin) 9 is provided on the semiconductor chip 2. When coating, the resin flows and spreads around, and as shown in FIG. 4, it may overlap with a part of the resin adhesive (silicone resin) 8 that joins the circuit board 3 to the lead frame 1. is there.

この場合に、ポリイミド樹脂はシリコーン樹脂と密着接合しないために、半導体装置の実使用状態でヒートサイクルなどの熱的ストレスが加わると、回路基板３の樹脂接着剤８と半導体チップ２の保護樹脂層９との重なり界面Ｐに隙間が発生し、さらにこの隙間を起点としてリードフレーム１と保護樹脂層９との界面に隙間が進展し、これが誘因となって半導体チップ２をリードフレーム１に接合している半田７にクラックが発生して半導体装置の信頼性を低下させるといった問題がある。   In this case, since the polyimide resin is not tightly bonded to the silicone resin, the resin adhesive 8 on the circuit board 3 and the protective resin layer on the semiconductor chip 2 when a thermal stress such as a heat cycle is applied in the actual use state of the semiconductor device. 9 and a gap is generated at the interface P between the lead frame 1 and the protective resin layer 9 starting from this gap, and this leads to the bonding of the semiconductor chip 2 to the lead frame 1. There is a problem that a crack is generated in the solder 7 and the reliability of the semiconductor device is lowered.

なお、前記のような問題は先記の特許文献１に開示されている構造でも完全に解消されず、さらに特許文献１の構造では保護樹脂層を２層とすることから工数が増えるほか、ワイヤが２層に成層した保護樹脂層の界面，および外側の保護樹脂層とモールド樹脂との間の界面を貫通している部分でワイヤが断線を引き起こし易くなるといった新たな課題も想定される。   The above-mentioned problem is not completely solved even in the structure disclosed in the above-mentioned Patent Document 1. Further, in the structure of Patent Document 1, the number of man-hours is increased because two protective resin layers are used. A new problem is also assumed such that the wire is likely to cause disconnection at a portion passing through the interface between the protective resin layer formed of two layers and the interface between the outer protective resin layer and the mold resin.

本発明は上記の点に鑑みなされたものであり、半導体チップの保護樹脂層を２層とした構成による前記課題の発生を避け、保護樹脂層を１層とした図３の構造を対象にその保護樹脂層を半導体チップにコーティングする際に、その樹脂が半導体チップの搭載領域を超えて隣接する回路基板の搭載領域まで流動拡散し、回路基板の樹脂接着剤層と重なり合うようになる事態を避けて製品の信頼性向上が図れるように改良した樹脂封止型半導体装置のパッケージ構造を提供することを目的とする。   The present invention has been made in view of the above points, and avoids the occurrence of the above-described problem due to the configuration in which the protective resin layer of the semiconductor chip is formed in two layers, and the structure of FIG. When coating the protective resin layer on the semiconductor chip, avoid the situation where the resin flows and diffuses beyond the mounting area of the semiconductor chip to the mounting area of the adjacent circuit board and overlaps the resin adhesive layer of the circuit board. It is an object of the present invention to provide a package structure of a resin-encapsulated semiconductor device improved so as to improve the reliability of a product.

上記目的を達成するために、本発明によれば、リードフレームの上面に半導体チップと回路部品を実装した回路基板とを並置搭載し、その相互間をワイヤ接続した上で周域をモールド樹脂により封止した樹脂封止型半導体装置で、前記半導体チップはフレームに半田マウントした上で該半導体チップに保護樹脂をコーティングし、回路基板は樹脂接着剤を用いてフレームに接合した構成になるものにおいて、
前記リードフレームの上面における半導体チップの搭載領域と絶縁基板の搭載領域との境界に、半導体チップおよびその周域にコーティングした保護樹脂が回路基板の搭載領域に流動拡散するのを阻止するダム部を設け（請求項１）、具体的には前記ダム部を次記のような態様で構成するものとする。 In order to achieve the above object, according to the present invention, a semiconductor chip and a circuit board on which circuit components are mounted are mounted in parallel on the upper surface of the lead frame, and the peripheral area is made of a mold resin after wire connection between them. In a sealed resin-sealed semiconductor device, the semiconductor chip is solder-mounted on a frame, and then the semiconductor chip is coated with a protective resin, and the circuit board is bonded to the frame using a resin adhesive. ,
At the boundary between the mounting area of the semiconductor chip and the mounting area of the insulating substrate on the upper surface of the lead frame, a dam portion for preventing the semiconductor chip and the protective resin coated on the peripheral area from flowing and diffusing into the mounting area of the circuit board Provided (Claim 1), specifically, the dam portion is configured in the following manner.

(1) ダム部がリードフレームに形成した凸条部である（請求項２）。   (1) The dam portion is a ridge formed on the lead frame (claim 2).

(2) 前記凸条部をリードフレームの裏面側から打ち出して形成する（請求項３）。   (2) The ridges are formed by punching from the back side of the lead frame (Claim 3).

上記の構成によれば、リードフレームに半田マウントした半導体チップに保護樹脂をコーティングする際に、チップの周域に流動する樹脂はリードフレーム上に形成したダム部に阻まれてそれ以上の広がりが阻止される。これにより、保護樹脂が回路基板の搭載領域に流れ込んで該基板の樹脂接着剤に重なり合うような事態を防いで製品の信頼性が向上する。また、そのダム部としての凸条部をリードフレームの裏面側から打ち出して形成することにより、金型を使って半導体装置をモールド成形する際に、モールド樹脂が凸条部の打ち出しによりフレームの裏面側に生じた加工穴を充填し、その投錨効果によってリードフレームとモールド樹脂との密着結合性を高めるとともに、前記ダム部との相乗効果により製品の信頼性をより一層高めることができる。   According to the above configuration, when the protective resin is coated on the semiconductor chip solder-mounted on the lead frame, the resin flowing in the peripheral area of the chip is blocked by the dam formed on the lead frame and further spreads. Be blocked. This prevents the protective resin from flowing into the mounting area of the circuit board and overlapping the resin adhesive on the circuit board, thereby improving the reliability of the product. In addition, by forming the ridge portion as the dam portion from the back surface side of the lead frame, when molding a semiconductor device using a mold, the mold resin is ejected from the back surface of the frame. The processing hole generated on the side is filled, and the anchoring effect of the lead frame and the mold resin is enhanced by the anchoring effect, and the reliability of the product can be further enhanced by the synergistic effect with the dam part.

上記のように本発明は、リードフレームの上面における半導体チップの搭載領域と絶縁基板の搭載領域との境界にダム部を設け、半導体チップおよびその周域にコーティングした保護樹脂が回路基板の搭載領域に流動拡散するのを阻止するようにしたものであり、以下その具体的実施例を図面に基づいて説明する。なお、各実施例の図中で図３，図４に対応する部材には同じ符号を付してその説明は省略する。   As described above, the present invention provides a dam portion at the boundary between the mounting area of the semiconductor chip and the mounting area of the insulating substrate on the upper surface of the lead frame, and the protective resin coated on the semiconductor chip and its peripheral area is mounted on the circuit board. In the following, a specific embodiment thereof will be described with reference to the drawings. In the drawings of the embodiments, members corresponding to those in FIGS. 3 and 4 are denoted by the same reference numerals and description thereof is omitted.

図１において、リードフレーム１の上面には、半導体チップ２の搭載領域と回路基板３の搭載領域との間を仕切るように双方の領域の境界に沿ってリブ状に突出する凸条部１ａが形成されている。この凸条部１ａは半導体チップ２に保護樹脂層（ポリイミド樹脂）９をコーティングする際に、その樹脂が回路基板３の搭載領域に流れ込むのを防ぐ堤防の役目を果たす。   In FIG. 1, on the upper surface of the lead frame 1, a protruding strip 1a protruding in a rib shape along the boundary between both regions so as to partition the mounting region of the semiconductor chip 2 and the mounting region of the circuit board 3 is formed. Is formed. When the semiconductor chip 2 is coated with a protective resin layer (polyimide resin) 9, the ridge portion 1 a serves as a bank to prevent the resin from flowing into the mounting area of the circuit board 3.

これにより、半導体チップ２にコーティングした保護樹脂層９は図示のように凸条部１ａの手前に止まり、図４のように回路基板２の搭載領域に流れ込んで樹脂接着剤（シリコーン樹脂）８の表面を覆うような状態を回避して製品の信頼性向上が図れる。   As a result, the protective resin layer 9 coated on the semiconductor chip 2 stops in front of the ridge portion 1a as shown, flows into the mounting area of the circuit board 2 as shown in FIG. It is possible to improve the reliability of the product by avoiding the state of covering the surface.

図２は本発明の請求項３に対応する実施例を示すものであり、図１に示した凸条部１ａは、リードフレーム１を裏面側から打ち出し加工して形成しており、１ｂは打ち出し加工でフレームの裏面に生じた穴である。   FIG. 2 shows an embodiment corresponding to claim 3 of the present invention. The protruding strip portion 1a shown in FIG. 1 is formed by stamping the lead frame 1 from the back side, and 1b is stamped. It is a hole generated on the back of the frame during processing.

これにより、続くモールド樹脂６の成形工程ではモールド樹脂が前記孔１ｂを充填するので、その投錨効果によりリードフレーム１とモールド樹脂６との密着結合性を高めることができ、実施例１で述べたダム部による効果と相乗して製品の信頼性をより一層向上できる。   As a result, in the subsequent molding process of the mold resin 6, the mold resin fills the holes 1b, so that the anchoring effect between the lead frame 1 and the mold resin 6 can be enhanced by the anchoring effect. In combination with the effect of the dam, the product reliability can be further improved.

本発明の実施例１に対応する半導体装置の要部の構成断面図Sectional drawing of the principal part of the semiconductor device corresponding to Example 1 of this invention 本発明の実施例２に対応する半導体装置の要部の構成断面図Sectional drawing of the principal part of the semiconductor device corresponding to Example 2 of this invention 樹脂封止型半導体装置の従来における構成断面図Cross-sectional view of a conventional resin-encapsulated semiconductor device 図３における要部部分の拡大図Enlarged view of the main part in FIG.

符号の説明Explanation of symbols

１ リードフレーム
１ａ 凸条部（ダム部）
１ｂ 凸条部の打ち出し加工孔
２ 半導体チップ
３ 回路基板
４ 回路部品
６ モールド樹脂
７ 半田
８ 樹脂接着剤
９ 保護樹脂層 1 Lead frame 1a Convex section (dam section)
1b Projection processing hole of ridge portion 2 Semiconductor chip 3 Circuit board 4 Circuit component 6 Mold resin 7 Solder 8 Resin adhesive 9 Protective resin layer

Claims (3)

リードフレームの上面に半導体チップと回路部品を実装した回路基板を並置搭載し、かつその相互間をワイヤ接続した上で周域をモールド樹脂で封止した樹脂封止型半導体装置であり、前記半導体チップはフレームに半田マウントした上で、該半導体チップに保護樹脂をコーティングし、回路基板は樹脂接着剤を用いてフレームに接合した構成になるものにおいて、
前記リードフレームの上面における半導体チップの搭載領域と絶縁基板の搭載領域との境界に、半導体チップおよびその周域にコーティングした保護樹脂が回路基板の搭載領域に流動拡散するのを阻止するダム部を設けたことを特徴とする樹脂封止型半導体装置。 A resin-encapsulated semiconductor device in which a circuit board on which a semiconductor chip and circuit components are mounted is mounted side by side on the upper surface of a lead frame, and the peripheral region is sealed with a mold resin after wire connection between them. The chip is solder-mounted on the frame, and the semiconductor chip is coated with a protective resin, and the circuit board is bonded to the frame using a resin adhesive.
At the boundary between the mounting area of the semiconductor chip and the mounting area of the insulating substrate on the upper surface of the lead frame, a dam portion for preventing the semiconductor chip and the protective resin coated on the peripheral area from flowing and diffusing into the mounting area of the circuit board A resin-encapsulated semiconductor device provided. 請求項１に記載の半導体装置において、ダム部がリードフレームに形成した凸条部であることを特徴とする樹脂封止型半導体装置。 2. The resin-encapsulated semiconductor device according to claim 1, wherein the dam portion is a ridge formed on the lead frame. 請求項２に記載の半導体装置において、凸条部をリードフレームの裏面側から打ち出して形成したことを特徴とする樹脂封止型半導体装置。 3. The resin-encapsulated semiconductor device according to claim 2, wherein the protrusion is formed by punching from the back side of the lead frame.
JP2003323986A 2003-09-17 2003-09-17 Resin-sealed semiconductor device Pending JP2005093635A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351737A (en) * 2005-06-15 2006-12-28 Hitachi Ltd Semiconductor power module
KR100691443B1 (en) 2005-11-16 2007-03-09 삼성전기주식회사 Flip chip package and fabrication method of the same
JP2009302526A (en) * 2008-05-16 2009-12-24 Denso Corp Electronic circuit device and manufacturing method thereof
JP2014154636A (en) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp Electronic component package and manufacturing method therefor
JPWO2016016970A1 (en) * 2014-07-30 2017-04-27 株式会社日立製作所 SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION DEVICE
CN112424919A (en) * 2018-07-20 2021-02-26 罗姆股份有限公司 Semiconductor device and method for manufacturing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351737A (en) * 2005-06-15 2006-12-28 Hitachi Ltd Semiconductor power module
JP4492448B2 (en) * 2005-06-15 2010-06-30 株式会社日立製作所 Semiconductor power module
KR100691443B1 (en) 2005-11-16 2007-03-09 삼성전기주식회사 Flip chip package and fabrication method of the same
JP2009302526A (en) * 2008-05-16 2009-12-24 Denso Corp Electronic circuit device and manufacturing method thereof
JP2014154636A (en) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp Electronic component package and manufacturing method therefor
JPWO2016016970A1 (en) * 2014-07-30 2017-04-27 株式会社日立製作所 SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND POWER CONVERSION DEVICE
CN112424919A (en) * 2018-07-20 2021-02-26 罗姆股份有限公司 Semiconductor device and method for manufacturing semiconductor device
CN112424919B (en) * 2018-07-20 2023-12-22 罗姆股份有限公司 Semiconductor device and method for manufacturing semiconductor device

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