JP2000077433A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JP2000077433A
JP2000077433A JP10247979A JP24797998A JP2000077433A JP 2000077433 A JP2000077433 A JP 2000077433A JP 10247979 A JP10247979 A JP 10247979A JP 24797998 A JP24797998 A JP 24797998A JP 2000077433 A JP2000077433 A JP 2000077433A
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor device
adhesive
semiconductor chip
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10247979A
Other languages
Japanese (ja)
Other versions
JP3923661B2 (en
Inventor
Tomoharu Horio
友春 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP24797998A priority Critical patent/JP3923661B2/en
Publication of JP2000077433A publication Critical patent/JP2000077433A/en
Application granted granted Critical
Publication of JP3923661B2 publication Critical patent/JP3923661B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent fitly a bonding agent from flowing in terminal parts on the surface of an insulating substrate by a simple means, without trouble such as let a semiconductor chip separate wide from the terminal parts on the surface of the substrate, in when where the chip is bonded on the surface of the substrate using the bonding agent. SOLUTION: A semiconductor device A is provided with an insulating substrate 1, having terminal parts 11 on the surface thereof and a semiconductor chip 3 bonded on the surface of this substrate 1 via a bonding agent 2 between the chip 3 and the substrate 1 and electrodes 30 formed on the chip 3 and the terminal parts 11 on the surface of the substrate 1 are connected with each other via wires W. In the semiconductor device A, projected or recessed step parts 13, which can prevent the bonding agent 2 from flowing in the parts 11 on the surface of the substrate 1 in the uncured state, are provided at the positions between the bonded place of the chip 3 to the surface of the substrate 1 and the parts 11 out of the position on the surface of the substrate 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【技術分野】本願発明は、合成樹脂製フィルムなどから
形成された絶縁基板上に接着剤を利用して半導体チップ
を接着したタイプの半導体装置、およびその製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is bonded to an insulating substrate formed of a synthetic resin film or the like using an adhesive, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】周知のとおり、樹脂パッケージ型の半導
体装置を製造する手段としては、金属製のリードフレー
ムを利用し、このリードフレーム上に半導体チップを搭
載する手段がある。ところが、この手段では、リードフ
レームの一部分を樹脂パッケージの外部に端子として露
出させる必要があるために、半導体装置全体の幅や厚み
のサイズが大きくなり易い。また、リードフレームは一
般にはかなり複雑な形状に形成する必要があり、そのコ
ストが高価であるために、最終的に得られる半導体装置
の製造コストも高価になってしまう。
2. Description of the Related Art As is well known, as a means for manufacturing a resin package type semiconductor device, there is a means for utilizing a metal lead frame and mounting a semiconductor chip on the lead frame. However, according to this means, since it is necessary to expose a part of the lead frame as a terminal outside the resin package, the width and thickness of the entire semiconductor device tend to increase. In addition, the lead frame generally needs to be formed in a considerably complicated shape, and the cost is high, so that the manufacturing cost of the finally obtained semiconductor device is also high.

【0003】そこで、従来では、リードフレームを利用
する手段に代えて、たとえば薄手の合成樹脂製フィルム
やその他の材質からなる絶縁基板を利用する手段も採用
されている。具体的には、この従来の手段は、図11に
示すように、たとえば薄手の合成樹脂製フィルムからな
る絶縁基板90の表面上に、接着剤91を介して半導体
チップ3eを接着するとともに、この半導体チップ3e
の複数の電極30eと絶縁基板90の複数の端子部92
とを金線などのワイヤWを介して電気的に接続する手段
である。このような手段によれば、絶縁基板90の原材
料コストを安価にすることができる。また、たとえば絶
縁基板90の裏面にハンダバンプ93を設けることによ
って、全体の幅や厚みを大きく嵩張らないようにして、
面実装型の半導体装置として仕上げることができる。
In view of the above, instead of using a lead frame, means using an insulating substrate made of, for example, a thin synthetic resin film or another material has been employed. Specifically, as shown in FIG. 11, this conventional means attaches the semiconductor chip 3e to the surface of an insulating substrate 90 made of, for example, a thin synthetic resin film via an adhesive 91, and Semiconductor chip 3e
Of the plurality of electrodes 30e and the plurality of terminal portions 92 of the insulating substrate 90
Are electrically connected via a wire W such as a gold wire. According to such means, the raw material cost of the insulating substrate 90 can be reduced. Also, for example, by providing solder bumps 93 on the back surface of the insulating substrate 90, the overall width and thickness are prevented from being large and bulky.
It can be finished as a surface-mount type semiconductor device.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来の手段では、次のような不具合を生じていた。
However, the above-mentioned conventional means has the following disadvantages.

【0005】すなわち、絶縁基板90の表面上に半導体
チップ3eを適切に接着させるには、平面視において接
着剤91が半導体チップ3eの外周にはみ出しを生じる
程度の広い範囲で接着剤91を絶縁基板90の表面部に
塗布する必要がある。接着剤91の塗布面積や塗布量が
少ないと、接着剤91の内部に空洞部が発生し易くな
り、たとえばハンダバンプ93をリフローさせようとし
てこのハンダバンプ93を加熱する際に、上記空洞部内
のエアが膨張する現象を生じ、適切ではないからであ
る。より具体的には、上記空洞部内のエアの膨張は、リ
ードフレームを用いる手段ではさほど大きな問題を生じ
させないものの、絶縁基板90としてたとえば軟質な合
成樹脂製が用いられている場合には、この絶縁基板90
が上記エアの膨張に起因して半導体チップ3eの周辺部
分において大きく膨らむように撓み変形する要因とな
り、ハンダバンプ93に位置ずれが生じるのである。
That is, in order to properly bond the semiconductor chip 3e to the surface of the insulating substrate 90, the adhesive 91 is applied to the insulating substrate 90 in a wide range such that the adhesive 91 protrudes to the outer periphery of the semiconductor chip 3e in plan view. 90 must be applied to the surface. When the application area or the application amount of the adhesive 91 is small, a cavity is easily generated inside the adhesive 91. For example, when the solder bump 93 is heated in order to reflow the solder bump 93, air in the cavity is generated. This is because it causes a phenomenon of expansion and is not appropriate. More specifically, the expansion of the air in the cavity does not cause a significant problem with the means using a lead frame. However, if the insulating substrate 90 is made of a soft synthetic resin, for example, Substrate 90
This is a factor that causes the peripheral portion of the semiconductor chip 3e to bend and deform so as to expand significantly due to the expansion of the air, and the solder bump 93 is displaced.

【0006】ところが、従来では、接着剤91を半導体
チップ3eの外周にはみ出す程度に塗布すると、この接
着剤91が硬化する以前の状態において、矢印Na方向
に流動し、端子部92の表面に流れ込む場合があった。
とくに、上記半導体装置の製造に際して、半導体チップ
3eの接着を確実にする手法としては、半導体チップ3
eをその上方から下向きに押圧するのが一般的であるた
めに、上記接着剤91は、端子部92の表面により流れ
込み易くなっていたのである。したがって、従来では、
端子部92の表面に接着剤が付着することに起因して、
この端子部92へのワイヤWのボンディング作業を適切
に行えなくなる場合があった。また、従来では、このよ
うな事態をできる限り防止する観点から、端子部92を
半導体チップ3eに余り接近させることができず、半導
体装置の小型化を図る上で一定の限界を生じていた。さ
らに、従来では、接着剤91が端子部92の表面に流れ
込まないようにするための接着剤91の塗布量や塗布位
置の管理も厳格に行う必要があった。
However, conventionally, when the adhesive 91 is applied to the extent that it protrudes to the outer periphery of the semiconductor chip 3 e, it flows in the direction of the arrow Na before the adhesive 91 is cured, and flows into the surface of the terminal portion 92. There was a case.
In particular, in the manufacture of the semiconductor device, as a method for ensuring the adhesion of the semiconductor chip 3e, the semiconductor chip 3e is used.
Since e is generally pressed downward from above, the adhesive 91 is more likely to flow into the surface of the terminal portion 92. Therefore, conventionally,
Due to the adhesion of the adhesive to the surface of the terminal portion 92,
In some cases, the operation of bonding the wire W to the terminal portion 92 cannot be performed properly. Further, conventionally, from the viewpoint of preventing such a situation as much as possible, the terminal portion 92 cannot be brought too close to the semiconductor chip 3e, and there is a certain limit in downsizing the semiconductor device. Furthermore, conventionally, it has been necessary to strictly control the amount and position of the adhesive 91 to prevent the adhesive 91 from flowing into the surface of the terminal portion 92.

【0007】本願発明は、このような事情のもとで考え
出されたものであって、絶縁基板の表面に接着剤を用い
て半導体チップを接着する場合に、半導体チップと絶縁
基板の端子部とを大きく離反させるようなことなく、接
着剤が絶縁基板の端子部に流れ込むことを簡易な手段に
よって適切に防止できるようにすることをその課題とし
ている。
The present invention was conceived under such circumstances, and when a semiconductor chip is bonded to the surface of an insulating substrate using an adhesive, the terminal portion between the semiconductor chip and the insulating substrate is formed. It is an object of the present invention to make it possible to appropriately prevent the adhesive from flowing into the terminal portion of the insulating substrate by a simple means without greatly separating the adhesive.

【0008】[0008]

【発明の開示】上記の課題を解決するため、本願発明で
は、次の技術的手段を講じている。
DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

【0009】本願発明の第1の側面によれば、半導体装
置が提供される。この半導体装置は、表面に端子部を有
する絶縁基板と、この絶縁基板の表面上に接着剤を介し
て接着された半導体チップとを具備しており、かつ上記
半導体チップの電極と上記絶縁基板の端子部とはワイヤ
を介して接続されている、半導体装置であって、上記絶
縁基板の表面上のうち、上記半導体チップの接着箇所と
上記端子部との間には、上記接着剤がその未硬化状態に
おいて上記絶縁基板の端子部に流れ込むことを防止可能
な凸状または凹状の段部が設けられていることに特徴づ
けられる。
According to a first aspect of the present invention, there is provided a semiconductor device. The semiconductor device includes an insulating substrate having a terminal portion on a surface thereof, and a semiconductor chip adhered on the surface of the insulating substrate via an adhesive, and the electrodes of the semiconductor chip and the insulating substrate. A terminal device is a semiconductor device connected via a wire, and the adhesive is not applied between the bonding portion of the semiconductor chip and the terminal portion on the surface of the insulating substrate. It is characterized in that a convex or concave step is provided which can prevent the insulating substrate from flowing into the terminal portion in the cured state.

【0010】上記段部は、上記絶縁基板の表面に設けた
レジスト層の一部を凸状に形成することにより、または
上記絶縁基板の表面もしくはその表面に設けたレジスト
層に凹溝を形成することにより設けられている構成とす
ることができる。
The step is formed by forming a part of the resist layer provided on the surface of the insulating substrate into a convex shape, or forming a concave groove on the surface of the insulating substrate or the resist layer provided on the surface. Accordingly, the configuration provided can be provided.

【0011】本願発明の第2の側面によれば、半導体装
置の製造方法が提供される。この半導体装置の製造方法
は、絶縁基板の表面上に接着剤を介して半導体チップを
接着する工程と、上記半導体チップの電極と上記絶縁基
板の表面の端子部とをワイヤ介して接続する工程とを有
している、半導体装置の製造方法であって、上記絶縁基
板として、上記半導体チップの接着箇所と上記端子部と
の間に、上記接着剤がその未硬化状態において上記絶縁
基板の端子部に流れ込むことを防止可能な凸状または凹
状の段部が設けられたものを用いることに特徴づけられ
る。
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes a step of bonding a semiconductor chip on a surface of an insulating substrate via an adhesive, and a step of connecting an electrode of the semiconductor chip and a terminal portion on a surface of the insulating substrate via a wire. A method of manufacturing a semiconductor device, comprising: as an insulating substrate, a terminal portion of the insulating substrate in an uncured state between the bonding portion of the semiconductor chip and the terminal portion in an uncured state. It is characterized by using a member provided with a convex or concave step portion capable of preventing the liquid from flowing into the substrate.

【0012】本願発明では、絶縁基板の表面上に塗布さ
れた接着剤が未硬化状態において絶縁基板の端子部の方
向に流れる事態を生じても、凸状または凹状の段部によ
ってその流れを堰き止めるなどして、上記接着剤が端子
部の方向へそれ以上流れないようにすることができる。
したがって、本願発明では、上記端子部の表面に接着剤
が不当に付着することを防止することができ、絶縁基板
上に搭載された半導体チップの電極と上記端子部とのワ
イヤ接続を適切に行うことができる。本願発明では、半
導体チップの接着箇所と絶縁基板の端子部との間の距離
を小さくした場合であっても、端子部の表面に接着剤が
流れ込まないようにできる。したがって、半導体装置全
体のサイズを従来よりも小さくすることが可能となる。
また、本願発明では、絶縁基板の表面に接着剤をかなり
多めに塗布しても端子部の表面に接着剤が流れ込むこと
を防止することが可能となるため、絶縁基板に対する接
着剤の塗布作業の管理も容易なものにできる。
In the present invention, even if the adhesive applied on the surface of the insulating substrate flows in the direction of the terminal portion of the insulating substrate in an uncured state, the flow is blocked by the convex or concave step. By stopping the adhesive, the adhesive can be prevented from flowing further in the direction of the terminal portion.
Therefore, in the present invention, it is possible to prevent the adhesive from being unduly attached to the surface of the terminal portion, and to appropriately perform the wire connection between the electrode of the semiconductor chip mounted on the insulating substrate and the terminal portion. be able to. According to the present invention, even when the distance between the bonding portion of the semiconductor chip and the terminal portion of the insulating substrate is reduced, the adhesive can be prevented from flowing into the surface of the terminal portion. Therefore, the size of the entire semiconductor device can be made smaller than before.
Further, according to the present invention, it is possible to prevent the adhesive from flowing into the surface of the terminal portion even if the adhesive is applied to the surface of the insulating substrate in a relatively large amount. It can be easily managed.

【0013】本願発明のその他の特徴および利点につい
ては、次の発明の実施の形態の説明から、より明らかに
なるであろう。
Other features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention.

【0014】[0014]

【発明の実施の形態】以下、本願発明の好ましい実施の
形態について、図面を参照しつつ具体的に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

【0015】図1は、本願発明に係る半導体装置の一例
を示す断面図である。図2は、図1に示す半導体装置の
平面透視図である。
FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention. FIG. 2 is a plan perspective view of the semiconductor device shown in FIG.

【0016】図1において、本実施形態の半導体装置A
は、いわゆるボールグリッドアレイタイプの樹脂パッケ
ージ型半導体装置として構成されたものである。この半
導体装置Aは、複数の端子部11を有する絶縁基板1、
レジスト層12、凸状の段部13、接着剤2、半導体チ
ップ3、封止樹脂4、および複数のハンダバンプ5を具
備して構成されている。
In FIG. 1, a semiconductor device A of the present embodiment is shown.
Is a so-called ball grid array type resin package type semiconductor device. The semiconductor device A includes an insulating substrate 1 having a plurality of terminals 11,
It comprises a resist layer 12, a convex step 13, an adhesive 2, a semiconductor chip 3, a sealing resin 4, and a plurality of solder bumps 5.

【0017】上記絶縁基板1は、たとえばポリイミドな
どの薄手の合成樹脂製フィルムからなり、その平面視の
形態は半導体チップ3よりも一廻り大きな矩形状であ
る。上記絶縁基板1の表面には、複数条の帯状の導電配
線10がパターン形成されている。これら複数条の導電
配線10は、たとえば銅箔によって形成されており、後
述する図3の説明から理解されるように、それらの一端
が上記複数の端子部11となっている。これら複数の端
子部11は、接着剤2の塗布領域(半導体チップ3の接
着箇所)を囲むように上記絶縁基板1の外周縁に沿って
並んでいる。上記複数のハンダバンプ5は、この半導体
装置Aを所望の位置へ面実装するのに利用されるもので
あり、上記複数条の導電配線10のそれぞれの他端部の
下面に接合しているとともに、上記絶縁基板1に設けら
れた貫通孔14を介して絶縁基板1の下方に突出してい
る。
The insulating substrate 1 is made of a thin synthetic resin film such as polyimide, for example, and has a rectangular shape that is slightly larger than the semiconductor chip 3 in plan view. A plurality of strip-shaped conductive wirings 10 are pattern-formed on the surface of the insulating substrate 1. The plurality of conductive wires 10 are formed of, for example, copper foil, and one end of each of the plurality of conductive wires 10 serves as the plurality of terminal portions 11 as will be understood from the description of FIG. The plurality of terminal portions 11 are arranged along the outer peripheral edge of the insulating substrate 1 so as to surround a region where the adhesive 2 is applied (a portion where the semiconductor chip 3 is bonded). The plurality of solder bumps 5 are used to surface-mount the semiconductor device A at a desired position, and are joined to the lower surfaces of the other end portions of the plurality of conductive wires 10, respectively. It protrudes below the insulating substrate 1 through a through hole 14 provided in the insulating substrate 1.

【0018】上記レジスト層12は、上記複数条の導電
配線10を保護するためのものであり、上記複数条の導
電配線10のうち上記複数の端子部11以外の領域を覆
うように絶縁基板1の表面の略全面にわたって設けられ
ている。上記段部13は、上記レジスト層12によって
形成されている。上記段部13は、上記レジスト層12
を形成するレジストのスクリーン印刷を複数回にわたっ
て繰り返して行い、上記レジスト層12の一部の厚みを
他の部分の厚みよりも大きくした凸状部分である。上記
段部13は、図2によく表れているように、平面視の全
体形状が中空矩形状となる筋状であり、上記複数の端子
部11の配置領域よりも内側の領域において半導体チッ
プ3の接着箇所を囲むように設けられている。
The resist layer 12 is for protecting the plurality of conductive wires 10, and covers the insulating substrate 1 so as to cover regions other than the plurality of terminal portions 11 of the plurality of conductive wires 10. Is provided over substantially the entire surface of the substrate. The step 13 is formed by the resist layer 12. The step 13 is formed of the resist layer 12
Are formed by repeating the screen printing of the resist for forming a plurality of times to form a part of the resist layer 12 having a thickness larger than that of the other parts. As shown in FIG. 2, the step portion 13 has a streak shape in which the overall shape in a plan view is a hollow rectangular shape, and the semiconductor chip 3 is located in a region inside the arrangement region of the plurality of terminal portions 11. Is provided so as to surround the bonding portion.

【0019】上記半導体チップ3は、たとえばICチッ
プであり、上記絶縁基板1のレジスト層12上に接着剤
2を介して接着されている。上記接着剤2としては、た
とえば熱硬化性のエポキシ樹脂系のものが適用されてい
る。上記半導体チップ3の上向きの主面に設けられた複
数の電極30と上記複数の端子部11とは、金線などの
ワイヤWを介して導電接続されている。上記封止樹脂4
は、上記半導体チップ3やワイヤWを封止して、これら
を保護するためのものである。
The semiconductor chip 3 is, for example, an IC chip, and is bonded on the resist layer 12 of the insulating substrate 1 via an adhesive 2. As the adhesive 2, for example, a thermosetting epoxy resin-based adhesive is applied. The plurality of electrodes 30 provided on the upward main surface of the semiconductor chip 3 and the plurality of terminal portions 11 are conductively connected via wires W such as gold wires. The above sealing resin 4
Is for sealing the semiconductor chip 3 and the wires W to protect them.

【0020】次に、上記半導体装置Aの製造方法の一例
について説明する。
Next, an example of a method for manufacturing the semiconductor device A will be described.

【0021】まず、上記絶縁基板1を形成するための部
材として、図3に示すような帯状のフィルム基板1aを
用いる。このフィルム基板1aの表面には、複数条の導
電配線10を1組とする導電配線パターンPが、このフ
ィルム基板1aの長手方向に一定間隔で多数組設けられ
ている。図3では、その図示を省略しているが、実際に
は、図4に示すように、上記フィルム基板1aの表面に
は上記複数条の導電配線10を覆うレジスト層12が設
けられている。また、このレジスト層12によって凸状
の段部13も形成されている。上記フィルム基板1aに
は、後にハンダバンプ5を接合させるための複数の貫通
孔14も設けられている。
First, as a member for forming the insulating substrate 1, a belt-like film substrate 1a as shown in FIG. 3 is used. A large number of conductive wiring patterns P each including a plurality of conductive wirings 10 are provided on the surface of the film substrate 1a at regular intervals in the longitudinal direction of the film substrate 1a. Although not shown in FIG. 3, in practice, as shown in FIG. 4, a resist layer 12 covering the plurality of conductive wires 10 is provided on the surface of the film substrate 1a. The resist layer 12 also forms a convex step 13. The film substrate 1a is also provided with a plurality of through holes 14 for joining the solder bumps 5 later.

【0022】図5に示すように、上記フィルム基板1a
のレジスト層12上には、接着剤2を塗布してから半導
体チップ3を接着する。この工程は、流動可能な液状ま
たはペースト状態で接着剤2を塗布してから、その上に
半導体チップ3を載置し、上記接着剤2を加熱しながら
上記半導体チップ3の上面を下方に向けて押圧しながら
行う。また、上記接着剤2は、半導体チップ3の周囲に
若干量だけはみ出すように多めに塗布し、接着剤2内に
空洞部が生じないようにする。したがって、上記接着剤
2が加熱によって硬化するまでの間は、図5および図6
の矢印N1に示すように、上記接着剤2がその四方に流
動する虞れがある。ところが、そのような事態を生じて
も、上記接着剤2は凸状の段部13によって堰き止めら
れる。したがって、上記接着剤2が上記段部13の外側
に位置する複数の端子部11まで流動しないようにでき
る。
As shown in FIG. 5, the film substrate 1a
The semiconductor chip 3 is bonded onto the resist layer 12 after applying the adhesive 2. In this step, after the adhesive 2 is applied in a flowable liquid or paste state, the semiconductor chip 3 is placed thereon, and the upper surface of the semiconductor chip 3 is turned downward while heating the adhesive 2. Perform while pressing. In addition, the adhesive 2 is applied to the periphery of the semiconductor chip 3 so as to protrude slightly by a small amount, so that a cavity is not formed in the adhesive 2. 5 and 6 until the adhesive 2 is cured by heating.
As shown by the arrow N1, there is a possibility that the adhesive 2 flows in all directions. However, even if such a situation occurs, the adhesive 2 is blocked by the convex step 13. Therefore, the adhesive 2 can be prevented from flowing to the plurality of terminal portions 11 located outside the step portion 13.

【0023】半導体チップ3の接着作業後には、各電極
30と各端子部11とにワイヤWのボンディング作業を
行う。次いで、金型を用いた樹脂成形工程によって上記
封止樹脂4を形成し、さらにはハンダバンプ5の形成作
業を行う。その後は、上記フィルム基板1aを絶縁基板
1とするように切断し、または打ち抜く。このような一
連の作業工程により、上記帯状のフィルム基板1aから
多数の半導体装置Aを順次生産することができる。
After the bonding operation of the semiconductor chip 3, the bonding operation of the wire W to each electrode 30 and each terminal portion 11 is performed. Next, the sealing resin 4 is formed by a resin molding process using a mold, and further, a solder bump 5 is formed. Thereafter, the film substrate 1a is cut or punched so as to be used as the insulating substrate 1. Through such a series of operation steps, a large number of semiconductor devices A can be sequentially produced from the belt-shaped film substrate 1a.

【0024】上記半導体装置Aでは、複数の端子部11
の表面に接着剤2が不当に付着しないようにできるため
に、これら複数の端子部11へのワイヤWのボンディン
グ作業を適切に行うことが可能である。とくに、上記凸
状の段部13は、接着剤2の塗布領域の四方全周を囲む
ように形成されているために、複数の端子部11の表面
が接着剤12によって汚れることをより確実に防止する
ことができる。
In the semiconductor device A, a plurality of terminals 11
The bonding operation of the wires W to the plurality of terminal portions 11 can be performed appropriately because the adhesive 2 can be prevented from being unduly attached to the surface of the wire. In particular, since the convex step portion 13 is formed so as to surround the entire periphery of the application region of the adhesive 2, the surface of the plurality of terminal portions 11 is more reliably prevented from being stained by the adhesive 12. Can be prevented.

【0025】図7は、本願発明に係る半導体装置の他の
例を示す断面図である。図8は、図7に示す半導体装置
に用いられている絶縁基板の導電配線パターンを示す要
部概略斜視図である。なお、図7以降の各図において
は、先の実施形態と同一部分は同一符号で示す。
FIG. 7 is a sectional view showing another example of the semiconductor device according to the present invention. FIG. 8 is a schematic perspective view of a main part showing a conductive wiring pattern of an insulating substrate used in the semiconductor device shown in FIG. 7 and the subsequent drawings, the same parts as those in the previous embodiment are denoted by the same reference numerals.

【0026】図7に示す半導体装置Aaは、絶縁基板1
の表面上のうち、半導体チップ3の接着箇所と複数の端
子部11との間に凸状の段部13Aが設けられている点
で、先の半導体装置Aと共通している。ただし、上記段
部13Aは、複数条の導電配線10A上にレジスト層1
2を形成することによって設けられている。より具体的
には、図8によく表れているように、上記各導電配線1
0Aは、ハンダバンプ5が接合される一端部10’から
その他端部である端子部11に到るまでの中間部の平面
視形状がジグザグ状、クランク状、あるいは略コの字状
などに蛇行した形状とされており、この導電配線10A
の形成部分は絶縁基板1自体の表面と比較すると凸状と
なっている。したがって、上記絶縁基板1の表面や各導
電配線10Aの表面に厚みが均一のレジスト層12を形
成すると、このレジスト層12のうち上記導電配線10
Aの形成箇所の高さが他の部分よりも高くなり、これが
1条または複数条の凸状の段部13Aとなっているので
ある。
The semiconductor device Aa shown in FIG.
The semiconductor device A is common in that a convex step 13A is provided between the bonding portion of the semiconductor chip 3 and the plurality of terminal portions 11 on the surface of the semiconductor device A. However, the step 13A is formed on the plurality of conductive wires 10A by the resist layer 1A.
2 is formed. More specifically, as shown well in FIG.
0A is a zigzag shape, a crank shape, or a substantially U-shaped shape in a plan view of an intermediate portion from one end 10 ′ to which the solder bump 5 is joined to the terminal 11, which is the other end. The conductive wiring 10A
Is formed in a convex shape as compared with the surface of the insulating substrate 1 itself. Therefore, when a resist layer 12 having a uniform thickness is formed on the surface of the insulating substrate 1 or the surface of each conductive wiring 10A, the conductive wiring 10
The height of the portion where A is formed is higher than the other portions, and this is one or a plurality of protruding steps 13A.

【0027】上記半導体装置Aaにおいても、上記段部
13Aによって接着剤2が複数の端子部11に向けて流
れることを防止することができ、各端子部11に対する
ワイヤボンディングを適切に行うことができる。このよ
うに、本願発明では、絶縁基板1上に形成される導電配
線パターンの厚みを利用して接着剤の流動を阻止するた
めの段部を設けた構成としてもかまわない。さらに、本
願発明では、導電配線パターンやレジスト層を利用する
ことなく、それ以外の物質または部材を絶縁基板上に設
けることよって凸状の段部を形成し、これによって接着
剤の流動を阻止するようにしてもかまわない。
Also in the semiconductor device Aa, the flow of the adhesive 2 toward the plurality of terminals 11 can be prevented by the steps 13A, and the wire bonding to each terminal 11 can be appropriately performed. . As described above, in the present invention, a configuration may be employed in which a step for preventing the flow of the adhesive is provided by utilizing the thickness of the conductive wiring pattern formed on the insulating substrate 1. Further, in the present invention, a convex step is formed by providing other substances or members on the insulating substrate without using the conductive wiring pattern or the resist layer, thereby preventing the flow of the adhesive. It does not matter.

【0028】図9は、本願発明に係る半導体装置の他の
例を示す断面図である。図10は、本願発明に係る半導
体装置の他の例を示す平面透視図である。
FIG. 9 is a sectional view showing another example of the semiconductor device according to the present invention. FIG. 10 is a perspective plan view showing another example of the semiconductor device according to the present invention.

【0029】図9に示す半導体装置Abでは、絶縁基板
1Bの表面に凹状の段部13Bが設けられている。この
段部13Bは、絶縁基板1Bの表面に凹溝を直接形成す
ることにより設けられたものであり、その平面視形状
は、たとえば先の半導体装置Aの段部13と同様に、複
数の端子部11の形成領域よりも内側において接着剤2
の塗布領域を囲む中空矩形状とされている。
In the semiconductor device Ab shown in FIG. 9, a concave step 13B is provided on the surface of the insulating substrate 1B. The step portion 13B is provided by directly forming a concave groove on the surface of the insulating substrate 1B, and has a plan view shape similar to that of the step portion 13 of the semiconductor device A described above, for example. Adhesive 2 inside the region where the portion 11 is formed
And a hollow rectangular shape surrounding the application region.

【0030】上記半導体装置Abでは、その製造過程に
おいて上記接着剤2が四方に流動する事態を生じたとき
には、この接着剤2を上記凹状の段部13B内に落とし
込むことによって、接着剤2がそれ以上複数の端子部1
1の方向に流動することを阻止し、または抑制すること
ができる。このように、本願発明でいう段部とは、凸状
のみらず、凹状であってもよい。むろん、凸状と凹状と
を組み合わせた段部であってもかまわない。本願発明で
いう段部の高さ寸法または深さ寸法については、接着剤
の粘性などとの関係もあり一概には特定することはでき
ず、その具体的な数値はとくに限定されるものではない
が、たとえば凸状の段部の段差を数十μmにした場合で
あっても、接着剤の流れをかなり阻止する効果が期待で
きる。
In the semiconductor device Ab, when the adhesive 2 flows in all directions in the manufacturing process, the adhesive 2 is dropped into the concave step 13B, whereby the adhesive 2 is removed. The plurality of terminals 1
Flow in one direction can be prevented or suppressed. Thus, the step portion in the present invention may be not only a convex shape but also a concave shape. Of course, a step portion combining a convex shape and a concave shape may be used. The height or depth of the step portion in the present invention cannot be specified unconditionally due to the relationship with the viscosity of the adhesive, etc., and specific numerical values are not particularly limited. However, even when the step of the convex step is set to several tens of μm, an effect of considerably preventing the flow of the adhesive can be expected.

【0031】絶縁基板に凹状の段部を形成する場合に
は、この段部の存在によって絶縁基板の強度に不足が生
じないように配慮する必要がある。したがって、凹状の
段部を形成する手段は、絶縁基板の厚みが比較的大きい
場合、あるいは絶縁基板を強度性に優れた材質とした場
合に適する。また、絶縁基板の材質をたとえばガラスエ
ポキシ樹脂製にした場合には、絶縁基板の表面に適当な
ジグを押し当てることによって凹状の段部を簡単に形成
することができ、その製造を容易なものにできる。上記
凹状の段部13Bは、絶縁基板1Bの表面に形成された
凹溝上にレジスト層12の一部が存在した構成となって
いる。ただし、本願発明では、これに代えて、たとえば
絶縁基板1B自体には凹溝を形成することなく、レジス
ト層12にのみ凹溝を形成し、これを凹状の段部として
もかまわない。さらに、本願発明では、凸状または凹状
の段部は、必ずしもレジスト層を利用して形成する必要
もなく、たとえば絶縁基板の表面に直接設けられた凹溝
をそのまま接着剤の流れを阻止するための段部としても
よい。
When a concave step is formed on the insulating substrate, it is necessary to take care that the presence of the step does not cause a shortage in the strength of the insulating substrate. Therefore, the means for forming the concave step is suitable when the thickness of the insulating substrate is relatively large or when the insulating substrate is made of a material having excellent strength. Also, when the material of the insulating substrate is made of, for example, glass epoxy resin, a concave step can be easily formed by pressing an appropriate jig against the surface of the insulating substrate, and the manufacturing thereof is easy. Can be. The concave step 13B has a configuration in which a part of the resist layer 12 exists on a concave groove formed on the surface of the insulating substrate 1B. However, in the present invention, instead of this, for example, a groove may be formed only in the resist layer 12 without forming a groove in the insulating substrate 1B itself, and this may be a concave step. Further, in the present invention, the convex or concave step does not necessarily need to be formed using a resist layer, and for example, a groove directly provided on the surface of the insulating substrate is used to directly block the flow of the adhesive. It is good also as a step part.

【0032】図10に示す半導体装置Acは、絶縁基板
1Cの複数の端子部11が半導体チップ3Cの左右両側
方にのみ設けられており、これら複数の端子部11と半
導体チップ3Cとの間には、凸状または凹状の段部13
C,13Cが平面視直線状の形態で設けられている。こ
の半導体装置Acでは、接着剤2が四方に広がる事態を
生じても、上記段部13C,13Cによって上記接着剤
2が複数の端子部11の表面に流れ込まないようにでき
る。また、同図の矢印N2方向に広がる接着剤について
は、上記段部13C,13Cによってその流れをくい止
めることはできないものの、その方向に接着剤が比較的
大きく広がってもとくに支障は生じない。このように、
本願発明でいう段部は、必ずしも半導体チップの接着箇
所の周囲を囲むように設けられている必要はない。段部
は、要は、少なくとも半導体チップの接着箇所と絶縁基
板の端子部との間に設けられていればよい。むろん、段
部の具体的な数も問わない。
In a semiconductor device Ac shown in FIG. 10, a plurality of terminal portions 11 of an insulating substrate 1C are provided only on the left and right sides of a semiconductor chip 3C, and between the plurality of terminal portions 11 and the semiconductor chip 3C. Is a convex or concave step 13
C and 13C are provided in a linear form in plan view. In the semiconductor device Ac, even when the adhesive 2 spreads in all directions, the adhesive 13 can be prevented from flowing into the surfaces of the plurality of terminals 11 by the steps 13C, 13C. Further, the flow of the adhesive spreading in the direction of arrow N2 in the figure cannot be stopped by the steps 13C, 13C, but there is no particular problem even if the adhesive spreads relatively large in that direction. in this way,
The step portion in the present invention need not always be provided so as to surround the periphery of the bonding portion of the semiconductor chip. What is essential is that the step portion is provided at least between the bonding portion of the semiconductor chip and the terminal portion of the insulating substrate. Of course, the specific number of steps does not matter.

【0033】本願発明は、上述の実施形態に限定されな
い。本願発明に係る半導体装置の各部の具体的な構成
は、種々に設計変更自在である。また、本願発明に係る
半導体装置の製造方法の各作業工程の具体的な構成も種
々に変更自在である。本願発明でいう絶縁基板とは、リ
ードフレームなどの金属やその他の導電部材からなる基
板を除外する概念であり、絶縁部材からなるものであれ
ば、その具体的な材質もとくに限定されるものではな
い。
The present invention is not limited to the above embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be variously changed in design. Further, the specific configuration of each operation step of the method for manufacturing a semiconductor device according to the present invention can be variously changed. The insulating substrate according to the present invention is a concept that excludes a substrate made of a metal or other conductive member such as a lead frame, and any material made of an insulating member is not particularly limited to a specific material. Absent.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本願発明に係る半導体装置の一例を示す断面図
である。
FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

【図2】図1に示す半導体装置の平面透視図である。FIG. 2 is a plan perspective view of the semiconductor device shown in FIG. 1;

【図3】絶縁基板を形成するためのフィルム基板の一例
を示す要部斜視図である。
FIG. 3 is a perspective view of an essential part showing an example of a film substrate for forming an insulating substrate.

【図4】レジスト層を有するフィルム基板の要部断面図
である。
FIG. 4 is a sectional view of a main part of a film substrate having a resist layer.

【図5】フィルム基板上に半導体チップを接着する工程
を示す要部断面図である。
FIG. 5 is a fragmentary cross-sectional view showing a step of bonding a semiconductor chip onto a film substrate.

【図6】図5の要部平面図である。FIG. 6 is a plan view of a main part of FIG. 5;

【図7】本願発明に係る半導体装置の他の例を示す断面
図である。
FIG. 7 is a sectional view showing another example of the semiconductor device according to the present invention.

【図8】図7に示す半導体装置に用いられている絶縁基
板の導電配線パターンを示す要部概略斜視図である。
8 is a schematic perspective view of a main part showing a conductive wiring pattern of an insulating substrate used in the semiconductor device shown in FIG. 7;

【図9】本願発明に係る半導体装置の他の例を示す断面
図である。
FIG. 9 is a sectional view showing another example of the semiconductor device according to the present invention.

【図10】本願発明に係る半導体装置の他の例を示す平
面透視図である。
FIG. 10 is a perspective plan view showing another example of the semiconductor device according to the present invention.

【図11】従来の半導体装置の一例を示す要部断面図で
ある。
FIG. 11 is a sectional view of a main part showing an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 絶縁基板 1a フィルム基板(絶縁基板) 2 接着剤 3,3C 半導体チップ 4 封止樹脂 5 ハンダバンプ 11 端子部 12 レジスト層 13,13A〜13C 段部 30 電極 W ワイヤ A,Aa〜Ac 半導体装置 DESCRIPTION OF SYMBOLS 1 Insulating substrate 1a Film substrate (insulating substrate) 2 Adhesive 3,3C semiconductor chip 4 Sealing resin 5 Solder bump 11 Terminal part 12 Resist layer 13,13A-13C Step part 30 Electrode W wire A, Aa-Ac Semiconductor device

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面に端子部を有する絶縁基板と、この
絶縁基板の表面上に接着剤を介して接着された半導体チ
ップとを具備しており、かつ上記半導体チップの電極と
上記絶縁基板の端子部とはワイヤを介して接続されてい
る、半導体装置であって、 上記絶縁基板の表面上のうち、上記半導体チップの接着
箇所と上記端子部との間には、上記接着剤がその未硬化
状態において上記絶縁基板の端子部に流れ込むことを防
止可能な凸状または凹状の段部が設けられていることを
特徴とする、半導体装置。
1. An insulating substrate having a terminal portion on a surface thereof, and a semiconductor chip adhered on the surface of the insulating substrate via an adhesive, wherein electrodes of the semiconductor chip and electrodes of the insulating substrate are provided. The terminal unit is a semiconductor device connected via a wire, and the adhesive is not applied between the bonding portion of the semiconductor chip and the terminal portion on the surface of the insulating substrate. A semiconductor device, comprising: a convex or concave step that can prevent a flow into a terminal portion of the insulating substrate in a cured state.
【請求項2】 上記段部は、上記絶縁基板の表面に設け
たレジスト層の一部を凸状に形成することにより、また
は上記絶縁基板の表面もしくはその表面に設けたレジス
ト層に凹溝を形成することにより設けられている、請求
項1に記載の半導体装置。
2. The method according to claim 1, wherein the step is formed by forming a part of the resist layer provided on the surface of the insulating substrate into a convex shape, or forming a concave groove on the surface of the insulating substrate or the resist layer provided on the surface thereof. The semiconductor device according to claim 1, wherein the semiconductor device is provided by being formed.
【請求項3】 絶縁基板の表面上に接着剤を介して半導
体チップを接着する工程と、上記半導体チップの電極と
上記絶縁基板の表面の端子部とをワイヤ介して接続する
工程とを有している、半導体装置の製造方法であって、 上記絶縁基板として、上記半導体チップの接着箇所と上
記端子部との間に、上記接着剤がその未硬化状態におい
て上記絶縁基板の端子部に流れ込むことを防止可能な凸
状または凹状の段部が設けられたものを用いることを特
徴とする、半導体装置の製造方法。
3. A step of bonding a semiconductor chip on the surface of the insulating substrate via an adhesive, and a step of connecting an electrode of the semiconductor chip and a terminal on the surface of the insulating substrate via a wire. The method of manufacturing a semiconductor device, wherein, as the insulating substrate, between the bonding portion of the semiconductor chip and the terminal portion, the adhesive flows into the terminal portion of the insulating substrate in an uncured state. A method of manufacturing a semiconductor device, comprising: using a semiconductor device provided with a convex or concave step portion capable of preventing the formation of a semiconductor device.
JP24797998A 1998-09-02 1998-09-02 Semiconductor device Expired - Fee Related JP3923661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24797998A JP3923661B2 (en) 1998-09-02 1998-09-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24797998A JP3923661B2 (en) 1998-09-02 1998-09-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2000077433A true JP2000077433A (en) 2000-03-14
JP3923661B2 JP3923661B2 (en) 2007-06-06

Family

ID=17171402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24797998A Expired - Fee Related JP3923661B2 (en) 1998-09-02 1998-09-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3923661B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079590A (en) * 2003-08-29 2005-03-24 Texas Instruments Inc Package for semiconductor device and its manufacturing method
US7479705B2 (en) 2003-08-28 2009-01-20 Renesas Technology Corp. Semiconductor device
CN111009504A (en) * 2018-10-05 2020-04-14 日本特殊陶业株式会社 Wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479705B2 (en) 2003-08-28 2009-01-20 Renesas Technology Corp. Semiconductor device
US7615872B2 (en) 2003-08-28 2009-11-10 Renesas Technology Corp. Semiconductor device
JP2005079590A (en) * 2003-08-29 2005-03-24 Texas Instruments Inc Package for semiconductor device and its manufacturing method
CN111009504A (en) * 2018-10-05 2020-04-14 日本特殊陶业株式会社 Wiring board

Also Published As

Publication number Publication date
JP3923661B2 (en) 2007-06-06

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