JP2010109253A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2010109253A
JP2010109253A JP2008281460A JP2008281460A JP2010109253A JP 2010109253 A JP2010109253 A JP 2010109253A JP 2008281460 A JP2008281460 A JP 2008281460A JP 2008281460 A JP2008281460 A JP 2008281460A JP 2010109253 A JP2010109253 A JP 2010109253A
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island
semiconductor element
connecting portion
lead
semiconductor device
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Masakazu Watanabe
昌和 渡辺
Masahiro Hatauchi
政弘 畑内
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Priority to JP2008281460A priority Critical patent/JP2010109253A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for preventing leakage of sticking agents used for sticking semiconductor elements to the outside, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device 10 includes: the semiconductor element 18 including electrodes disposed on a main surface; a lead 12A electrically connected to the semiconductor element 18 and partially led to the outside; and an encapsulating resin 24 integrally covering the semiconductor element 18 and the lead 12A. A tab 20 continues via a slender connection section 22, and is exposed outside from the encapsulating resin 24. An island 14 and the periphery of the connection section 22 project in a thickness direction to form a projection 30. Also, the upper surface of the connection section 22 is recessed to provide a stepped portion 38, and the stepped portion 38 reaches the projection 30 provided at both the sides of the connection section 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、特に、固着材を介してアイランドに固着された半導体素子が一体的に樹脂封止される半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which semiconductor elements fixed to an island through a fixing material are integrally sealed with a resin, and a manufacturing method thereof.

図８の斜視図を参照して、従来型の半導体装置１００の構成を説明する。   The configuration of the conventional semiconductor device 100 will be described with reference to the perspective view of FIG.

従来型の半導体装置１００は、アイランド１１４と、アイランド１１４の上面に固着された半導体素子１１８と、リード１１２Ａ−１１２Ｃと、半導体素子１１８と各リードとを接続する金属細線１３０と、これらの構成要素を一体的に被覆する封止樹脂１２４とを主要に具備している。   The conventional semiconductor device 100 includes an island 114, a semiconductor element 118 fixed to the upper surface of the island 114, leads 112A-112C, a thin metal wire 130 connecting the semiconductor element 118 and each lead, and components thereof. And a sealing resin 124 that integrally covers the main body.

アイランド１１４およびリード１１２Ａ−１１２Ｃは、厚みが０．５ｍｍ程度の金属板から形成される。アイランド１１４は、上面に半導体素子１１８が固着可能な大きさであり、その下面は封止樹脂１２４から外部に露出している。また、リード１１２Ａ−１１２Ｃの一端はアイランド１１４に接近し、他端は封止樹脂１２４から外部に露出して外部接続電極として機能している。   The island 114 and the leads 112A to 112C are formed from a metal plate having a thickness of about 0.5 mm. The island 114 has such a size that the semiconductor element 118 can be fixed to the upper surface thereof, and the lower surface thereof is exposed to the outside from the sealing resin 124. Also, one end of the leads 112A-112C approaches the island 114, and the other end is exposed to the outside from the sealing resin 124 and functions as an external connection electrode.

アイランド１１４には、細長い２つの連結部１２２を経由して、タブ１２０が連続している。そして、タブ１２０は、封止樹脂１２４の側面から外部に突出しており、固着材を用いて半導体装置１００を実装基板等に実装する際に、固着材が塗布される状況を容易に確認するために設けられている。即ち、半田等の固着材を用いて半導体素子１００を実装基板に実装したときに、アイランド１１４の底面に塗布した半田がタブ１２０まで回り込んだら、アイランド１１４の底面が半田により良好に固着されたと判断する。一方、アイランド１１４の裏面に塗布された半田がタブ１２０まで回り込まずに視覚的に確認されなければ、半田による接合が不良であると判断される。   A tab 120 is continuous with the island 114 via two elongated connecting portions 122. The tab 120 protrudes to the outside from the side surface of the sealing resin 124, so that when the semiconductor device 100 is mounted on a mounting substrate or the like using the fixing material, the situation where the fixing material is applied can be easily confirmed. Is provided. That is, when the semiconductor element 100 is mounted on the mounting substrate using a fixing material such as solder, if the solder applied to the bottom surface of the island 114 reaches the tab 120, the bottom surface of the island 114 is fixed firmly by the solder. to decide. On the other hand, if the solder applied to the back surface of the island 114 does not go around to the tab 120 and is not visually confirmed, it is determined that the solder joint is defective.

上記した構成の半導体装置は、例えば以下の特許文献１に記載されている。
特開２００２−０７６１９５号公報 The semiconductor device having the above-described configuration is described in Patent Document 1 below, for example.
JP 2002-076195 A

しかしながら、上記した構成の半導体装置１００では、半導体素子１１８の固着に用いられる半田が外部に漏出してしまう問題があった。具体的には、アイランド１１４の上面に塗布された半田を溶融させて半導体素子１１８を固着すると、半導体素子１１８の重みにより液状の半田が周囲に流出する。そして、一部の半田は連結部１１２の上面を経由してタブ１２０まで流出する場合がある。タブ１２０は封止樹脂１２４から外部に突出する部位であるので、タブ１２０まで流出した半田は外部に露出して外観劣化を招く。また、半田として鉛半田が採用された場合、有害物質である鉛が装置の外部に露出することになるので不良となる。   However, the semiconductor device 100 having the above-described configuration has a problem that the solder used for fixing the semiconductor element 118 leaks to the outside. Specifically, when the solder applied to the upper surface of the island 114 is melted and the semiconductor element 118 is fixed, liquid solder flows out to the surroundings due to the weight of the semiconductor element 118. A part of the solder may flow out to the tab 120 via the upper surface of the connecting portion 112. Since the tab 120 protrudes from the sealing resin 124 to the outside, the solder that has flowed out to the tab 120 is exposed to the outside and causes appearance deterioration. Further, when lead solder is adopted as the solder, lead, which is a harmful substance, is exposed to the outside of the apparatus, resulting in a failure.

本発明は、上述した問題を鑑みて成されたものである。本発明の主な目的は、半導体素子の固着に用いられる固着材の外部への漏出が防止された半導体装置およびその製造方法を提供することにある。   The present invention has been made in view of the above-described problems. A main object of the present invention is to provide a semiconductor device in which leakage of a fixing material used for fixing a semiconductor element to the outside is prevented, and a manufacturing method thereof.

本発明の半導体装置は、アイランドと、熱により流れ出す接合材を介して前記アイランドの主面に固着された半導体素子と、前記半導体素子と接続されて一端が外部に露出するリードと、前記アイランド、前記半導体素子および前記リードの一部を被覆する封止樹脂と、連結部を介して前記アイランドと連続して前記封止樹脂の側面から外部に露出するタブと、前記連結部の両側辺および前記アイランド周囲を連続して厚み方向に突出させた突出部と、前記連結部の両側辺に設けられた前記突出部に到達するように前記連結部の上面を窪ませた段差部と、を備えたことを特徴とする。   The semiconductor device of the present invention includes an island, a semiconductor element fixed to the main surface of the island via a bonding material that flows out by heat, a lead connected to the semiconductor element and having one end exposed to the outside, the island, A sealing resin covering a part of the semiconductor element and the lead; a tab continuously exposed to the island through a connecting portion; and a tab exposed to the outside from a side surface of the sealing resin; Protruding portions that continuously protrude around the island in the thickness direction, and a stepped portion in which the upper surface of the connecting portion is recessed so as to reach the protruding portions provided on both sides of the connecting portion. It is characterized by that.

本発明の半導体装置は、アイランドと、ロウ材を介して前記アイランドの主面に固着された半導体素子と、前記半導体素子と接続されて一端が外部に露出するリードと、前記リードが設けられた一側辺と対向する他方の側辺に一体で延在し、前記アイランドの幅よりも狭い少なくとも１本の連結部と、前記連結部と一体で前記側辺と平行に延在されるタブと、前記アイランド、前記半導体素子、前記リードの一部および前記連結部の少なくとも一部を覆う封止樹脂と、を有し、前記連結部の両側辺には、上方に向かって突出部が設けられると共に、２つの前記突出部の間には、前記突出部よりも下方に位置する表面部があり、前記連結部が設けられた所の近傍に位置する半導体素子の周囲には、前記ロウ材がはみ出して設けられ、前記はみ出したロウ材の流れ出し流路と成る前記表面部および前記表面部と突出部の境界近傍には、前記表面部から前記境界を越えて前記突出部に到る凹み部が設けられることを特徴する。   The semiconductor device of the present invention is provided with an island, a semiconductor element fixed to the main surface of the island via a brazing material, a lead connected to the semiconductor element and having one end exposed to the outside, and the lead A tab that extends integrally with the other side opposite the one side, is narrower than the width of the island, and a tab that is integral with the connection and extends parallel to the side. And a sealing resin that covers at least a part of the island, the semiconductor element, the lead, and the connecting portion, and protruding portions are provided upward on both sides of the connecting portion. In addition, there is a surface portion located below the two protruding portions between the two protruding portions, and the brazing material is disposed around the semiconductor element located near the connection portion. Provided to protrude, said protrusion And a boundary vicinity of the projecting portion and the surface portion and the surface portion comprising the outflow passage of the brazing material, which characterized by leading recess in the projecting portion beyond the boundary from the surface portion is provided.

本発明の半導体装置の製造方法は、連結部を介してタブが連続するアイランドと前記アイランドに一端が接近するリードとを含み、前記アイランドおよび前記連結部の周辺部を厚み方向に突出させた突出部が設けられたリードフレームを用意する工程と、前記連結部の両端に設けられた前記突出部に到達するように、前記連結部の上面を窪ませて段差部を設ける工程と、固着材を介して前記アイランドの上面に半導体素子を固着し、前記半導体素子と前記リードとを接続する工程と、前記半導体素子、前記アイランドおよび前記リードを封止樹脂により被覆する工程と、を備えたことを特徴とする。   According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: an island having tabs connected through a connecting portion; and a lead having one end approaching the island; A step of providing a lead frame provided with a portion, a step of providing a stepped portion by recessing the upper surface of the connecting portion so as to reach the protruding portions provided at both ends of the connecting portion, and a fixing material. A step of fixing a semiconductor element to the upper surface of the island and connecting the semiconductor element and the lead; and a step of covering the semiconductor element, the island, and the lead with a sealing resin. Features.

本発明では、アイランドとタブとを連続させる連結部の上面を部分的に窪ませて段差部を設け、この段差部を、連結部の両端部を厚み方向に突出させた突出部まで到達させている。従って、アイランドの上面に塗布された液状の半田が、連結部の上面に進入しても、段差部により半田のそれ以上の漏出が抑制される。このことにより、液状の半田はタブまで進行しないので、半田の外部への露出が防止される。特に半田として鉛半田を採用した場合、有害物質である鉛の装置外面への露出が防止されるので、外部の環境に悪影響を及ぼさない半導体装置が提供される。   In the present invention, a stepped portion is provided by partially denting the upper surface of the connecting portion that connects the island and the tab, and this stepped portion is made to reach the protruding portion where both end portions of the connecting portion protrude in the thickness direction. Yes. Therefore, even if the liquid solder applied to the upper surface of the island enters the upper surface of the connecting portion, further leakage of the solder is suppressed by the step portion. As a result, the liquid solder does not travel to the tab, so that exposure of the solder to the outside is prevented. In particular, when lead solder is used as the solder, exposure of lead, which is a harmful substance, to the outer surface of the device is prevented, so that a semiconductor device that does not adversely affect the external environment is provided.

図１を参照して半導体装置１０の構成を説明する。図１（Ａ）は半導体装置１０の斜視図であり、図１（Ｂ）は一部を拡大した平面図であり、図１（Ｃ）は断面図である。尚、図１（Ａ）では、アイランドの構造を明示するために、半導体素子１８とリード１２Ａ等とを接続する接続板を不図示としている。   The configuration of the semiconductor device 10 will be described with reference to FIG. 1A is a perspective view of the semiconductor device 10, FIG. 1B is a partially enlarged plan view, and FIG. 1C is a cross-sectional view. In FIG. 1A, a connection plate for connecting the semiconductor element 18 and the leads 12A and the like is not shown in order to clearly show the island structure.

図１（Ａ）を参照して、半導体装置１０は、半導体素子１８と、半導体素子１８が実装されるアイランド１４と、半導体素子１８とリード１２Ａ等とを接続する接続板（不図示）と、これらを一体的に封止する封止樹脂２４と、連結部２２を介してアイランド１４と連続して封止樹脂２４の側面から外部に露出するタブ２０とを主要に有する。   Referring to FIG. 1A, a semiconductor device 10 includes a semiconductor element 18, an island 14 on which the semiconductor element 18 is mounted, a connection plate (not shown) that connects the semiconductor element 18 and the leads 12A, and the like. It mainly includes a sealing resin 24 that integrally seals them, and a tab 20 that is exposed to the outside from the side surface of the sealing resin 24 continuously to the island 14 via the connecting portion 22.

半導体素子１８としては、ＭＯＳＦＥＴ（Ｍｅｔａｌ−Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）、バイポーラトランジスタ、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）、ＩＣ、ダイオード等を採用可能である。例えば、半導体素子１８としてＭＯＳＦＥＴが採用されると、半導体素子１８の上面にゲート電極およびソース電極が設けられ、下面にドレイン電極が設けられる。また、半導体素子１８としてバイポーラトランジスタが採用されると、半導体素子１８の上面にベース電極およびエミッタ電極が設けられ、下面にコレクタ電極が設けられる。半導体素子１８の上面に形成された２つの電極は、各々が接続板を経由してリード１２Ａ、１２Ｂと接続される。半導体素子１８の裏面は、半田（ロウ材）等の導電性の固着材を介してアイランド１４の上面に固着される。ここで、半導体素子１８の裏面が電極として機能しない場合は、エポキシ樹脂等を主材料する絶縁性の固着材を介して半導体素子１８がアイランド１４の上面に固着されても良い。   As the semiconductor element 18, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), an IC, a diode, or the like can be adopted. For example, when a MOSFET is employed as the semiconductor element 18, a gate electrode and a source electrode are provided on the upper surface of the semiconductor element 18, and a drain electrode is provided on the lower surface. When a bipolar transistor is employed as the semiconductor element 18, a base electrode and an emitter electrode are provided on the upper surface of the semiconductor element 18, and a collector electrode is provided on the lower surface. The two electrodes formed on the upper surface of the semiconductor element 18 are each connected to the leads 12A and 12B via the connection plate. The back surface of the semiconductor element 18 is fixed to the upper surface of the island 14 via a conductive fixing material such as solder (brazing material). Here, when the back surface of the semiconductor element 18 does not function as an electrode, the semiconductor element 18 may be fixed to the upper surface of the island 14 through an insulating fixing material mainly made of epoxy resin or the like.

アイランド１４は、厚みが０．５ｍｍ程度の銅等から成る導電箔をエッチング加工または打ち抜き加工することで形成される。アイランド１４の平面的な大きさは、上面に実装される半導体素子１８よりも若干大きい程度である。例えば、アイランド１４の平面的なサイズは５．５ｍｍ×５．５ｍｍ程度である。   The island 14 is formed by etching or punching a conductive foil made of copper or the like having a thickness of about 0.5 mm. The planar size of the island 14 is slightly larger than the semiconductor element 18 mounted on the upper surface. For example, the planar size of the island 14 is about 5.5 mm × 5.5 mm.

タブ２０は、アイランド１４と連続して形成されて、封止樹脂２４の下面および側面から外部に露出する部位である。ここでは、タブ２０は２つの細長い連結部２２を介してアイランド１４と連続しており、タブ２０の下面とアイランド１４の下面は同一平面上に位置している。タブ２０は、半導体装置１０を実装する際に、実装に用いられる半田等の接合材が、アイランド１４に良好に溶着されたか否かを判断するために設けられた部位である。即ち、半導体素子１８を実装するときは、アイランド１４の下面と共にタブ２０の下面および側面にも固着材が付着される。そして、タブ２０に付着した固着材が目視にて良好に確認されたら、アイランド１４の下面にも良好に固着材が塗布されたと判断される。一方、タブ２０に付着した固着材が目視にて確認されない場合は、アイランド１４の下面に充分に接合材が塗布されていないこととなり、接合不良と判断される。   The tab 20 is a portion that is formed continuously with the island 14 and is exposed to the outside from the lower surface and side surfaces of the sealing resin 24. Here, the tab 20 is continuous with the island 14 via two elongated connecting portions 22, and the lower surface of the tab 20 and the lower surface of the island 14 are located on the same plane. The tab 20 is a part provided to determine whether or not a bonding material such as solder used for mounting is favorably welded to the island 14 when the semiconductor device 10 is mounted. That is, when the semiconductor element 18 is mounted, the fixing material is attached to the lower surface and side surfaces of the tab 20 as well as the lower surface of the island 14. And if the fixing material adhering to the tab 20 is confirmed satisfactorily by visual observation, it is determined that the fixing material has also been successfully applied to the lower surface of the island 14. On the other hand, when the fixing material adhering to the tab 20 is not visually confirmed, the bonding material is not sufficiently applied to the lower surface of the island 14 and it is determined that the bonding is defective.

リード１２Ａ等は、アイランド１４と同様の方法により形成され、一端がアイランド１４の近傍に位置し、他端が封止樹脂２４から外部に露出している。ここでは、３本のリード１２Ａ、１２Ｂ、１２Ｃが設けられる。リード１２Ａ、１２Ｂのアイランド１４に接近する方の端部は幅広の接続部２６Ａ、２６Ｂとされている。このように、各リードの先端部を幅広の接続部とすることで、この接続部の上面に半田を介して接続板が安定して載置される。   The leads 12A and the like are formed by the same method as that for the island 14, and one end is located near the island 14 and the other end is exposed to the outside from the sealing resin 24. Here, three leads 12A, 12B, and 12C are provided. The ends of the leads 12A and 12B that are close to the island 14 are wide connecting portions 26A and 26B. Thus, by making the tip of each lead a wide connecting portion, the connecting plate is stably placed on the upper surface of the connecting portion via solder.

更に、リード１２Ａ、１２Ｂの他端は、封止樹脂２４の側面から外部に露出してガルウイング状に折り曲げ加工され、下面の一部分はアイランド１４の下面と同一平面上に位置している（図１（Ｃ）参照）。また、中央に位置するリード１２Ｃは、アイランド１４から連続して外部に導出しているが、リード１２Ａやリード１２Ｂよりも短く切断されている。このリード１２Ｃは、他のリード１２Ａ等と同様に接続手段として用いられても良いし用いられなくても良い。   Further, the other ends of the leads 12A and 12B are exposed to the outside from the side surface of the sealing resin 24 and bent into a gull wing shape, and a part of the lower surface is located on the same plane as the lower surface of the island 14 (FIG. 1). (See (C)). The lead 12C located at the center is continuously led out from the island 14, but is cut shorter than the lead 12A and the lead 12B. This lead 12C may or may not be used as a connecting means like other leads 12A and the like.

一例として、半導体素子１８がＭＯＳＦＥＴの場合は、リード１２Ａがソース電極と接続され、リード１２Ｂがゲート電極と接続され、アイランド１４がドレイン電極と接続される。更に、封止樹脂２４に被覆される部分のリード１２Ａ、１２Ｂ、１２Ｃの上面を部分的に窪ませて溝１３が設けられている。この様に溝１３を設けることにより、この部分と封止樹脂２４との密着する面積が広がり、リード１２Ａ等と封止樹脂２４との密着強度が向上される。   As an example, when the semiconductor element 18 is a MOSFET, the lead 12A is connected to the source electrode, the lead 12B is connected to the gate electrode, and the island 14 is connected to the drain electrode. Further, the grooves 13 are provided by partially denting the upper surfaces of the leads 12A, 12B, 12C of the portions covered with the sealing resin 24. By providing the groove 13 in this manner, the area where this portion and the sealing resin 24 are in close contact with each other increases, and the adhesive strength between the lead 12A and the like and the sealing resin 24 is improved.

封止樹脂２４は、半導体素子１８、リード１２Ａ、１２Ｂ、アイランド１４等を一括して被覆して全体を機械的に支持する機能を有する。封止樹脂２４の材料としては、熱硬化性樹脂または熱可塑性樹脂から成り、放熱性を向上させるために粒子状または繊維状のフィラーが混入されても良い。   The sealing resin 24 has a function of covering the semiconductor element 18, the leads 12 </ b> A and 12 </ b> B, the island 14, and the like collectively and mechanically supporting the whole. The sealing resin 24 is made of a thermosetting resin or a thermoplastic resin, and particulate or fibrous fillers may be mixed in order to improve heat dissipation.

接続板１６Ａは、図１（Ｃ）を参照して、厚みが例えば０．１ｍｍ程度の銅等から成る金属板をプレス加工して成形されたものであり、半導体素子１８とリード１２Ａとを電気的に接続する接続手段として機能している。接続板１６Ａ等は、クリップと称される場合もある。ここで、半導体素子１８とリードとを接続する接続手段としては、接続板に替えて金属細線が採用されても良い。   Referring to FIG. 1C, the connection plate 16A is formed by pressing a metal plate made of copper or the like having a thickness of, for example, about 0.1 mm, and electrically connects the semiconductor element 18 and the lead 12A. It functions as a connection means to connect. The connection plate 16A or the like may be referred to as a clip. Here, as a connection means for connecting the semiconductor element 18 and the lead, a thin metal wire may be employed instead of the connection plate.

半導体素子１８の下面の電極は、接合材２８を介して半導体素子１８のソース電極に固着されている。接合材２８としては、導電性ペーストまたは半田が採用される。ここで、導電性ペーストとは銀等から成る粉状の導電材料を絶縁性接着材に混入させたものであり、半田としては高温半田または低温半田が採用される。ここで使用される半田は、溶融温度が２８０℃乃至３５０℃程度の高温半田で、鉛の含有率が９０％程度である。   The electrode on the lower surface of the semiconductor element 18 is fixed to the source electrode of the semiconductor element 18 through the bonding material 28. As the bonding material 28, a conductive paste or solder is employed. Here, the conductive paste is obtained by mixing a powdery conductive material made of silver or the like into an insulating adhesive, and high-temperature solder or low-temperature solder is used as the solder. The solder used here is a high-temperature solder having a melting temperature of about 280 ° C. to 350 ° C., and the lead content is about 90%.

図１（Ａ）を参照して、アイランド１４の周辺端部を上方に突出させて額縁状の突出部３０が形成されている。アイランド１４の厚みが、０．５ｍｍの場合、突出部３０が突出する高さは例えば０．０５ｍｍ〜０．２ｍｍ程度である。突出部３０は連結部２２の両端にも連続して形成され、連結部２２とタブ２０とが連続する箇所まで連続して形成される。突出部３０は、半導体素子１８の実装に用いられる接合材の外部への流出を防止する機能を備えている。更には、突出部３０を設けてアイランド１４の形状を異形形状とすることで、アイランド１４と封止樹脂２４とが密着する強度が向上される。   With reference to FIG. 1 (A), the peripheral edge part of the island 14 protrudes upwards, and the frame-shaped protrusion part 30 is formed. When the thickness of the island 14 is 0.5 mm, the height at which the protruding portion 30 protrudes is, for example, about 0.05 mm to 0.2 mm. The protruding portion 30 is also formed continuously at both ends of the connecting portion 22 and is continuously formed up to the place where the connecting portion 22 and the tab 20 are continuous. The protruding portion 30 has a function of preventing the bonding material used for mounting the semiconductor element 18 from flowing out to the outside. Furthermore, the intensity | strength which the island 14 and the sealing resin 24 adhere | attach is improved by providing the protrusion part 30 and making the shape of the island 14 into an irregular shape.

図１（Ｂ）を参照して、連結部２２の上面をプレス加工（コイニング加工）することにより、段差部３８（凹み部）が形成されている。段差部３８は、連結部２２の上面平坦部だけではなく、両端に形成された突出部３０に到るまで形成される。即ち、連結部２２の上面平坦部および突出部３０の一部分に対して、プレス加工を施すことにより段差部３８が形成される。換言すると、段差部３８は、連結部２２上面の表面部に加えて、段差部２２の表面部と突出部３０との境界を越えて突出部３０に到る様に形成されている。   With reference to FIG. 1 (B), the level | step-difference part 38 (recessed part) is formed by pressing the upper surface of the connection part 22 (coining process). The stepped portion 38 is formed not only on the upper flat portion of the connecting portion 22 but also on the protruding portions 30 formed at both ends. That is, the stepped portion 38 is formed by pressing the upper flat portion of the connecting portion 22 and a part of the protruding portion 30. In other words, the stepped portion 38 is formed so as to reach the protruding portion 30 beyond the boundary between the surface portion of the stepped portion 22 and the protruding portion 30 in addition to the surface portion of the upper surface of the connecting portion 22.

この様にすることで、アイランド１４と連続する連結部２２の上面と、タブ２０と連続する連結部２２の上面とが、段差部３８によって分断される。従って、アイランド１４に塗布された液状の半田がアイランドから連結部２２に進入しても、半田自身に作用する表面張力により連結部２２の手前にて半田の進行がストップする。更に、進入した半田が段差部３８に貯留されることによっても、半田のタブ２０への進入が防止される。   By doing so, the stepped portion 38 divides the upper surface of the connecting portion 22 continuous with the island 14 and the upper surface of the connecting portion 22 continuous with the tab 20. Therefore, even if the liquid solder applied to the island 14 enters the connecting portion 22 from the island, the progress of the solder stops before the connecting portion 22 due to the surface tension acting on the solder itself. Furthermore, the entry of solder into the tab 20 is also prevented by storing the solder that has entered into the stepped portion 38.

更に、本実施の形態では、図１（Ｃ）を参照して、複数のプレス加工により段差部３８を形成しているので、段差部３８の断面形状は単純な矩形形状ではなく、段差を備えた異形形状を呈している。このことにより、複雑な形状を呈する段差部３８に強固に封止樹脂２４が嵌合し、アイランド１４と封止樹脂２４との密着強度が向上される。   Furthermore, in this embodiment, with reference to FIG. 1C, the stepped portion 38 is formed by a plurality of press processes, so that the cross-sectional shape of the stepped portion 38 is not a simple rectangular shape but includes a stepped portion. It has an irregular shape. As a result, the sealing resin 24 is firmly fitted to the stepped portion 38 having a complicated shape, and the adhesion strength between the island 14 and the sealing resin 24 is improved.

次に、図２を参照して、上述した構成の半導体装置１０が実装基板４０に実装された構成を説明する。図２（Ａ）は実装構造を示す断面図であり、図２（Ｂ）は半導体装置１０の裏面を示す平面図である。   Next, a configuration in which the semiconductor device 10 having the above-described configuration is mounted on the mounting substrate 40 will be described with reference to FIG. 2A is a cross-sectional view illustrating the mounting structure, and FIG. 2B is a plan view illustrating the back surface of the semiconductor device 10.

図２（Ａ）を参照して、上述した構成の半導体装置１０は、半田等の固着材４４を介して、実装基板４０に実装される。実装基板４０の上面には所定形状の導電パターン４２がパターニングされており、溶融された液状または半固形状の導電性の固着材４４（例えば半田）を用いて、半導体装置１０は、パッド形状の導電パターン４２に固着される。ここでは、リード１２Ａおよびアイランド１４の下面が、導電パターン４２に固着されている。   Referring to FIG. 2A, the semiconductor device 10 having the above-described configuration is mounted on the mounting substrate 40 via a fixing material 44 such as solder. A conductive pattern 42 having a predetermined shape is patterned on the upper surface of the mounting substrate 40, and the semiconductor device 10 is pad-shaped using a molten liquid or semi-solid conductive fixing material 44 (for example, solder). It is fixed to the conductive pattern 42. Here, the lower surface of the lead 12 </ b> A and the island 14 is fixed to the conductive pattern 42.

封止樹脂２４の側面から外部に導出するリード１２Ａの下面は、パッド状の導電パターン４２に接合されている。ここで、外部に導出する部分のリード１２Ａはガルウイング形状に折り曲げ加工されており、リード１２Ａの端部の下面は、封止樹脂２４の下面と同一平面上に位置している。係る構成は、リード１２Ｂも同様である。   The lower surface of the lead 12 </ b> A led out from the side surface of the sealing resin 24 is bonded to the pad-like conductive pattern 42. Here, the lead 12 </ b> A that leads to the outside is bent into a gull wing shape, and the lower surface of the end of the lead 12 </ b> A is located on the same plane as the lower surface of the sealing resin 24. This configuration is the same for the lead 12B.

上面に半導体素子１８が実装されたアイランド１４の下面は、封止樹脂２４の下面から外部に露出して、固着材４４を介して導電パターン４２に接合されている。また、連結部２２を経由して連結されたタブ２０の下面及び側面にも、固着材４４が付着している。このように、アイランド１４と連結されて封止樹脂２４から側方に突出するタブ２０を設け、このタブ２０に付着した固着材４４を目視確認することで、アイランド１４の下面の接合状況の良否をある程度判断することができる。即ち、タブ２０の側方まで固着材４４が付着していたら、アイランド１４の下面にも充分に固着材４４が行き渡っていると判断できる。一方、タブ２０に固着材４４が付着していなければ、アイランド１４の下方にも固着材４４が充分に行き渡っておらず、接続不良が発生していると予測される。   The lower surface of the island 14 on which the semiconductor element 18 is mounted on the upper surface is exposed to the outside from the lower surface of the sealing resin 24 and is bonded to the conductive pattern 42 via the fixing material 44. Further, the fixing material 44 is also attached to the lower surface and the side surface of the tab 20 connected via the connecting portion 22. In this way, the tabs 20 that are connected to the islands 14 and project laterally from the sealing resin 24 are provided, and the bonding material 44 attached to the tabs 20 is visually confirmed, so that the bonding state of the lower surface of the islands 14 is good or bad. Can be judged to some extent. That is, if the fixing material 44 adheres to the side of the tab 20, it can be determined that the fixing material 44 has sufficiently spread to the lower surface of the island 14. On the other hand, if the fixing material 44 does not adhere to the tab 20, the fixing material 44 does not sufficiently spread below the island 14 and it is predicted that a connection failure has occurred.

図２（Ｂ）を参照して、封止樹脂２４の裏面には、アイランド１４の裏面とタブ２０の裏面が連結部２２を経由して連続した状態で露出している。従って、アイランド１４の裏面に半田から成る固着材が充分に塗布されたら、塗布された半田は連結部２２を経由してタブ２０まで行き渡る。   Referring to FIG. 2B, the back surface of the island 14 and the back surface of the tab 20 are exposed on the back surface of the sealing resin 24 via the connecting portion 22. Accordingly, when the fixing material made of solder is sufficiently applied to the back surface of the island 14, the applied solder reaches the tab 20 via the connecting portion 22.

次に、図３から図７を参照して、上記した構成の半導体装置の製造方法を説明する。   Next, a method for manufacturing the semiconductor device having the above-described configuration will be described with reference to FIGS.

先ず、図３を参照して、所定形状のリードフレーム４６を用意する。図３（Ａ）はリードフレーム４６全体を示す平面図であり、図３（Ｂ）はリードフレーム４６に含まれるユニット５０を示す斜視図である。   First, referring to FIG. 3, a lead frame 46 having a predetermined shape is prepared. FIG. 3A is a plan view showing the entire lead frame 46, and FIG. 3B is a perspective view showing a unit 50 included in the lead frame 46.

図３（Ａ）を参照して、リードフレーム４６の外形は短冊形状であり、枠状の外枠４８の内部に複数個のユニット５０が形成されている。ここでユニットとは、１つの半導体装置を構成する部位の集まりである。図では、額縁状の外枠４８と連結された９個のユニット５０が示されているが、外枠４８の内部にマトリックス状に多数個のユニット５０が設けられても良い。   Referring to FIG. 3A, the outer shape of the lead frame 46 is a strip shape, and a plurality of units 50 are formed inside a frame-shaped outer frame 48. Here, a unit is a group of parts constituting one semiconductor device. In the figure, nine units 50 connected to the frame-shaped outer frame 48 are shown, but a large number of units 50 may be provided in a matrix in the outer frame 48.

図３（Ｂ）を参照して、１つのユニット５０は、１つのアイランド１４と、アイランド１４に一端が接近する複数のリードとから成る。アイランド１４は、上面に半導体素子が載置可能な大きさ（例えば５．５ｍｍ×５．５ｍｍ程度）であり、細長い形状の連結部２２を経由して、タブ２０が連続している。また、タブ２０が連続する辺に対向するアイランド１４の辺からはリード１２Ｃが一体的に延在して、外枠４８と連続している。即ち、リード１２Ｃは、アイランド１４を外枠４８に固定する為の吊りリードとして機能している。リード１２Ａは、一端がアイランド１４に接近して他端は外枠４８に連結されている。そして、アイランド１４に接近するリード１２Ａの端部を部分的に幅広とすることで接続部２６Ａが形成されている。この構成はリード１２Ｂも同様であり、アイランド１４側の端部には幅広の接続部２６Ｂが形成され、一方の端部は外枠４８と連続している。   Referring to FIG. 3B, one unit 50 includes one island 14 and a plurality of leads whose one end approaches the island 14. The island 14 has a size (for example, about 5.5 mm × 5.5 mm) on which the semiconductor element can be placed on the upper surface, and the tabs 20 are continuous via the elongated connecting portion 22. Further, the lead 12 </ b> C extends integrally from the side of the island 14 facing the side where the tab 20 is continuous, and is continuous with the outer frame 48. That is, the lead 12 </ b> C functions as a suspension lead for fixing the island 14 to the outer frame 48. One end of the lead 12 </ b> A approaches the island 14 and the other end is connected to the outer frame 48. Then, the connecting portion 26A is formed by partially widening the end portion of the lead 12A approaching the island 14. This configuration is the same for the lead 12B. A wide connection portion 26B is formed at the end portion on the island 14 side, and one end portion is continuous with the outer frame 48.

更に、図３（Ｂ）を参照して、アイランド１４に対してプレス加工を施し、アイランド１４の周辺部を部分的に額縁状に突出させて突出部３０を形成する。突出部３０は、連結部２２の両側にも形成されており、連結部２２とタブ２０とが連続する箇所に到るまで、突出部３０は形成されている。この突出部３０は、溶融した液状の半田を用いて半導体素子をアイランド１４の上面に固着する工程にて、液状の半田がアイランド１４から外側に漏出することを防止する機能を備えている。   Further, referring to FIG. 3 (B), the island 14 is pressed, and the peripheral portion of the island 14 is partially projected in a frame shape to form the protruding portion 30. The protruding portion 30 is also formed on both sides of the connecting portion 22, and the protruding portion 30 is formed until reaching the location where the connecting portion 22 and the tab 20 are continuous. The protrusion 30 has a function of preventing the liquid solder from leaking out of the island 14 in the process of fixing the semiconductor element to the upper surface of the island 14 using molten liquid solder.

次に、図４および図５を参照して、連結部２２の上面を部分的に窪ませることにより段差部を形成する。本工程では、複数回のプレス加工（コイニング加工）を施すことにより、第１段差部３８Ａ（第１の凹み部）および第２段差部３８Ｂ（第２の凹み部）から成る段差部３８を構成している。ここで、１回のプレス加工により段差部３８を設けることも可能であるが、複数回のプレス加工により異形形状の段差部を設けることにより、後の工程に形成される封止樹脂と段差部３８との接続強度を向上させることができる。   Next, referring to FIG. 4 and FIG. 5, the stepped portion is formed by partially denting the upper surface of the connecting portion 22. In this step, the stepped portion 38 composed of the first stepped portion 38A (first recessed portion) and the second stepped portion 38B (second recessed portion) is configured by performing press processing (coining processing) a plurality of times. is doing. Here, it is possible to provide the stepped portion 38 by a single press working, but by providing a stepped portion having an irregular shape by a plurality of press workings, a sealing resin and a stepped portion formed in a later step The connection strength with 38 can be improved.

図４を参照して、先ず、連結部２２の上面に第１段差部３８Ａを形成する。図４（Ａ）−図４（Ｃ）は図４（Ｄ）のＸ−Ｘ’線に於ける断面図である。   With reference to FIG. 4, first, a first step portion 38 </ b> A is formed on the upper surface of the connecting portion 22. 4A to 4C are cross-sectional views taken along line X-X ′ of FIG.

ここでは、図４（Ａ）および図４（Ｂ）を参照して、プレス用の金型６６を用いて上方から連結部２２をプレス加工している。金型６６によるプレス加工は、連結部２２の上面だけではなく、連結部２２の両端に設けた突出部３０に対しても部分的に行われている。連結部２２の厚みが０．５ｍｍの場合、金型６６により連結部２２の表面がプレス加工される厚みは例えば、０．０５ｍｍ〜０．２ｍｍ程度である。   Here, with reference to FIG. 4 (A) and FIG. 4 (B), the connection part 22 is press-processed from upper direction using the metal mold | die 66 for a press. The press working by the mold 66 is partially performed not only on the upper surface of the connecting portion 22 but also on the protruding portions 30 provided at both ends of the connecting portion 22. When the thickness of the connection part 22 is 0.5 mm, the thickness by which the surface of the connection part 22 is pressed by the mold 66 is, for example, about 0.05 mm to 0.2 mm.

図４（Ｃ）および図４（Ｄ）を参照して、本工程により形成される第１段差部３８Ａは、左側の突出部３０から右側の突出部３０に渡り連続して形成されている。そして、図４（Ｄ）を参照して、アイランド１４と連続する連結部の上面と、タブ２０と連続する連結部の上面とは、第１段差部３８Ａにより分断されている形となる。従って、後の工程にてアイランド１４の上面に塗布された液状の半田がアイランド１４側から連結部２２に進入しても、第１段差部３８Ａにより、連結部２２の上面が分断されているので、連結部２２の上面を経由して半田がタブ２０に進入することが抑制されている。   Referring to FIGS. 4C and 4D, the first stepped portion 38A formed by this process is continuously formed from the left protruding portion 30 to the right protruding portion 30. Then, referring to FIG. 4D, the upper surface of the connecting portion continuous with island 14 and the upper surface of the connecting portion continuous with tab 20 are separated by first stepped portion 38A. Therefore, even if liquid solder applied to the upper surface of the island 14 in the later step enters the connecting portion 22 from the island 14 side, the upper surface of the connecting portion 22 is divided by the first stepped portion 38A. The solder is prevented from entering the tab 20 via the upper surface of the connecting portion 22.

図５を参照して、次に、金型７０を用いた更なるプレス加工を行うことにより、第２段差部３８Ｂを形成する。ここで、図５（Ａ）−図５（Ｃ）の断面図は、図５（Ｄ）のＹ−Ｙ’線における断面図である。   With reference to FIG. 5, next, the 2nd level | step-difference part 38B is formed by performing the further press work using the metal mold | die 70. FIG. Here, the cross-sectional views of FIGS. 5A to 5C are cross-sectional views taken along line Y-Y ′ of FIG.

図５（Ａ）および図５（Ｂ）を参照して、金型７０により連結部２２を上面から再びプレス加工する。金型７０は、図５（Ｄ）に示す縦方向に関して図４（Ａ）に示した金型６６よりも長く、横方向に関して金型６６よりも短い。また、金型７０が連結部２２の上面をプレスする深さは、金型６６の半分程度またはそれ以下である。更にまた、金型７０は第１段差部３８Ａよりも幅が広いので、金型７０は、第１段差部３８Ａ付近の連結部２２の上面をプレス加工することになる。   Referring to FIGS. 5A and 5B, the connecting portion 22 is pressed again from the upper surface by the mold 70. The mold 70 is longer than the mold 66 shown in FIG. 4A in the vertical direction shown in FIG. 5D and shorter than the mold 66 in the horizontal direction. The depth at which the mold 70 presses the upper surface of the connecting portion 22 is about half of the mold 66 or less. Furthermore, since the mold 70 is wider than the first stepped portion 38A, the mold 70 presses the upper surface of the connecting portion 22 near the first stepped portion 38A.

従って、図５（Ｃ）および図５（Ｄ）を参照して、段差部３８は、第１段差部３８Ａと第２段差部３８Ｂとから構成される。第１段差部３８Ａは、上記したように、連結部２２の両側に形成された突出部３０に到るまで形成されている。第２段差部３８Ｂは突出部３０までは到達せず、連結部２２上面の中央部付近を窪ませて形成されている。   Therefore, referring to FIG. 5C and FIG. 5D, the stepped portion 38 is composed of a first stepped portion 38A and a second stepped portion 38B. As described above, the first stepped portion 38 </ b> A is formed up to the projecting portions 30 formed on both sides of the connecting portion 22. The second stepped portion 38B does not reach the protruding portion 30, and is formed by recessing the vicinity of the central portion of the upper surface of the connecting portion 22.

更に、金型７０によるプレス加工が行われることにより、第１段差部３８Ａの側面は、上部の方が内側に傾斜する傾斜面となっている。このことにより、後の工程に形成される封止樹脂が、第１段差部３８Ａの傾斜面と嵌合して、アイランド１４と封止樹脂との密着強度が向上される。   Furthermore, by performing press working with the mold 70, the side surface of the first stepped portion 38A is an inclined surface in which the upper portion is inclined inward. As a result, the sealing resin formed in the subsequent process is fitted to the inclined surface of the first stepped portion 38A, and the adhesion strength between the island 14 and the sealing resin is improved.

図６を参照して、次に、アイランド１４の上面に半導体素子１８を実装し、更に半導体素子１８の電極とリード１２Ａ、１２Ｂとを、接続板１６Ａ、１６Ｂを介して接続する。図６（Ａ）は本工程を示す平面図であり、図６（Ｂ）はその斜視図である。   Referring to FIG. 6, next, the semiconductor element 18 is mounted on the upper surface of the island 14, and the electrodes of the semiconductor element 18 and the leads 12A, 12B are connected via the connection plates 16A, 16B. FIG. 6A is a plan view showing this step, and FIG. 6B is a perspective view thereof.

先ず、アイランド１４の上面に半田クリームを介して、半導体素子１８を実装する。半導体素子１８としては、上記したように、ＭＯＳＦＥＴ、バイポーラトランジスタ、ＩＧＢＴ、ＩＣ、ダイオード等が採用される。ここでは、一例としてＭＯＳＦＥＴが半導体素子１８として採用され、上面にソース電極およびゲート電極が設けられ、裏面はドレイン電極が形成されている。   First, the semiconductor element 18 is mounted on the upper surface of the island 14 via a solder cream. As described above, a MOSFET, a bipolar transistor, an IGBT, an IC, a diode, or the like is employed as the semiconductor element 18. Here, as an example, a MOSFET is employed as the semiconductor element 18, a source electrode and a gate electrode are provided on the upper surface, and a drain electrode is formed on the rear surface.

更に、固着材を介して接続板１６Ａ、１６Ｂを固着する。具体的には、図６（Ｂ）を参照して、半導体素子１８と接続部２６Ａとが接続板１６Ａを介して接続され、半導体素子１８と接続部２６Ｂとが接続板１６Ｂを介して接続される。各接続板の接続は、半導体素子１８と同様に半田クリームを用いて行われる。   Further, the connection plates 16A and 16B are fixed through a fixing material. Specifically, referring to FIG. 6B, the semiconductor element 18 and the connection portion 26A are connected via the connection plate 16A, and the semiconductor element 18 and the connection portion 26B are connected via the connection plate 16B. The Each connection plate is connected using solder cream in the same manner as the semiconductor element 18.

半導体素子１８および接続板の載置が終了した後は、リフロー炉を用いて過熱することにより、各半田クリームを溶融して半導体素子１８および接続板を固着する。   After the placement of the semiconductor element 18 and the connection plate is completed, the solder cream is melted by using a reflow furnace to fix the semiconductor element 18 and the connection plate.

このとき、半導体素子１８の裏面に塗布された半田クリームが溶融して液状の半田となり、半導体素子１８の厚みにより押し出された液状の半田がアイランド１４から外部に漏出しようとする。本形態では、アイランド１４の周辺端部に突出部３０を設けているので、この突出部３０によりアイランド１４から外部への漏出が抑制される。   At this time, the solder cream applied to the back surface of the semiconductor element 18 melts to become liquid solder, and the liquid solder pushed out due to the thickness of the semiconductor element 18 tends to leak out from the island 14. In this embodiment, since the protrusion 30 is provided at the peripheral edge of the island 14, leakage from the island 14 to the outside is suppressed by the protrusion 30.

また、アイランド１４と連結部２２とが連続する部分には、突出部３０が設けられていないので、液状の半田が連結部２２の上面に進入する。しかしながら、本実施形態では、連結部２２の両側に設けられた突出部３０に到るまで、連結部２２の上面を窪ませた段差部３８を形成している。従って、大部分の半田のタブ２０側への進行は、半田自身に加わる表面張力により段差部３８の手前でストップする。また、それ以上進行しても、凹状の段差部３８に半田が貯留されることにより、タブ２０への半田の進入が抑制されている。   Further, since the projecting portion 30 is not provided at a portion where the island 14 and the connecting portion 22 are continuous, the liquid solder enters the upper surface of the connecting portion 22. However, in the present embodiment, the stepped portion 38 is formed in which the upper surface of the connecting portion 22 is recessed until reaching the protruding portions 30 provided on both sides of the connecting portion 22. Therefore, the progression of most solder toward the tab 20 side stops before the step portion 38 due to the surface tension applied to the solder itself. Further, even if it proceeds further, the solder is stored in the concave stepped portion 38, so that the entry of the solder into the tab 20 is suppressed.

図７を参照して、次に、半導体素子１８等が被覆されるように樹脂封止を行う。図７（Ａ）は本工程を示す断面図であり、図７（Ｂ）は本工程を経たリードフレーム４６を示す平面図である。   Referring to FIG. 7, next, resin sealing is performed so as to cover semiconductor element 18 and the like. FIG. 7A is a cross-sectional view showing this step, and FIG. 7B is a plan view showing the lead frame 46 that has undergone this step.

図７（Ａ）を参照して、本工程では、モールド金型５８を用いて樹脂封止を行う。このモールド金型５８は、上金型６０と下金型６２とから成り、両者を当接させることで、封止樹脂が注入されるキャビティ６４が形成される。樹脂封止の方法としては、熱硬化性樹脂を用いるトランスファーモールドが採用される。   Referring to FIG. 7A, in this step, resin sealing is performed using a mold die 58. The mold 58 is composed of an upper mold 60 and a lower mold 62, and a cavity 64 into which a sealing resin is injected is formed by bringing them into contact with each other. As a resin sealing method, a transfer mold using a thermosetting resin is employed.

具体的な封止方法は、先ず、半導体素子１８が上面に実装されたアイランド１４とリード１２Ａの端部を、キャビティ６４に収納させる。次に、モールド金型５８に設けたゲート（不図示）からキャビティ６４の内部に封止樹脂を注入して、アイランド１４、半導体素子１８、接続板１６Ａおよびリード１２Ａを樹脂封止する。更に本工程では、連結部２２の上面に設けた段差部３８に封止樹脂が充填されて嵌合するので、アイランド１４と封止樹脂との密着強度が向上される。   As a specific sealing method, first, the island 14 on which the semiconductor element 18 is mounted on the upper surface and the end portion of the lead 12 </ b> A are accommodated in the cavity 64. Next, a sealing resin is injected into the cavity 64 from a gate (not shown) provided in the mold 58, and the island 14, the semiconductor element 18, the connection plate 16A, and the lead 12A are resin-sealed. Further, in this step, since the sealing resin is filled and fitted into the stepped portion 38 provided on the upper surface of the connecting portion 22, the adhesion strength between the island 14 and the sealing resin is improved.

ここでは、アイランド１４の下面を外部に露出させるために、下金型６２の内壁にアイランド１４の下面が当接している。更にまた、タブ２０の上面および側面は、封止樹脂により被覆されないので、金型のキャビティ６４の外部に位置している。   Here, in order to expose the lower surface of the island 14 to the outside, the lower surface of the island 14 is in contact with the inner wall of the lower mold 62. Furthermore, since the upper surface and the side surface of the tab 20 are not covered with the sealing resin, they are located outside the cavity 64 of the mold.

キャビティ６４の内部への樹脂の注入が終了した後は、モールド金型５８から樹脂封止体を取り出す。また、封止樹脂として採用された樹脂が熱硬化性樹脂である場合は、加熱硬化の工程が必要となる。   After the injection of the resin into the cavity 64 is completed, the resin sealing body is taken out from the mold die 58. Further, when the resin employed as the sealing resin is a thermosetting resin, a heat curing step is required.

図７（Ｂ）に樹脂封止が終了した後のリードフレーム４６を示す。ここでは、リードフレーム４６に設けられた各ユニット５０が一括して同時に樹脂封止される。   FIG. 7B shows the lead frame 46 after the resin sealing is completed. Here, the units 50 provided on the lead frame 46 are collectively resin-sealed at the same time.

本工程が終了した後は、打ち抜き加工を行うことでリードフレーム４６から各ユニット５０を分離し、分離された半導体装置を、例えば実装基板上に実装する。また、外部に露出するリード１２Ａ等の酸化を防止するために、リード１２Ａの表面を半田メッキ等のメッキ膜により被覆する。   After this process is completed, each unit 50 is separated from the lead frame 46 by punching, and the separated semiconductor device is mounted on a mounting substrate, for example. Further, in order to prevent oxidation of the lead 12A and the like exposed to the outside, the surface of the lead 12A is covered with a plating film such as solder plating.

以上の工程により、図１に構造を示す半導体装置１０が製造される。   Through the above steps, the semiconductor device 10 whose structure is shown in FIG. 1 is manufactured.

本発明の半導体装置を示す図であり、（Ａ）は斜視図であり、（Ｂ）は拡大された平面図であり、（Ｃ）は断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) is a perspective view, (B) is the expanded top view, (C) is sectional drawing. 本発明の半導体装置を示す図であり、（Ａ）は断面図であり、（Ｂ）は半導体装置の裏面を示す平面図である。1A is a cross-sectional view of a semiconductor device according to the present invention, and FIG. 2B is a plan view illustrating a back surface of the semiconductor device. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は平面図であり、（Ｂ）は斜視図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is a perspective view. 本発明の半導体装置の製造方法を示す図であり、（Ａ）−（Ｃ）は断面図であり、（Ｄ）は平面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A)-(C) is sectional drawing, (D) is a top view. 本発明の半導体装置の製造方法を示す図であり、（Ａ）−（Ｃ）は断面図であり、（Ｄ）は平面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A)-(C) is sectional drawing, (D) is a top view. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は平面図であり、（Ｂ）は斜視図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is a perspective view. 本発明の半導体装置の製造方法を示す図であり、（Ａ）は断面図であり、（Ｂ）は平面図である。It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is sectional drawing, (B) is a top view. 背景技術の半導体装置を示す斜視図である。It is a perspective view which shows the semiconductor device of background art.

符号の説明Explanation of symbols

１０ 半導体装置
１２Ａ，１２Ｂ，１２Ｃ リード
１４ アイランド
１６Ａ，１６Ｂ 接続板
１８ 半導体素子
２０ タブ
２２ 連結部
２４ 封止樹脂
２６Ａ，２６Ｂ 接続部
２８ 接合材
３０ 突出部
３８ 段差部
３８Ａ 第１段差部
３８Ｂ 第２段差部
４０ 実装基板
４２ 導電パターン
４４ 固着材
４６ リードフレーム
４８ 外枠
５０ ユニット
５８ モールド金型
６０ 上金型
６２ 下金型
６４ キャビティ
６６ 金型
７０ 金型
DESCRIPTION OF SYMBOLS 10 Semiconductor device 12A, 12B, 12C Lead 14 Island 16A, 16B Connection board 18 Semiconductor element 20 Tab 22 Connection part 24 Sealing resin 26A, 26B Connection part 28 Bonding material 30 Protrusion part 38 Step part 38A 1st step part 38B 2nd Stepped portion 40 Mounting substrate 42 Conductive pattern 44 Adhering material 46 Lead frame 48 Outer frame 50 Unit 58 Mold die 60 Upper die 62 Lower die 64 Cavity 66 Mold 70 Mold

Claims (10)

アイランドと、
熱により流れ出す接合材を介して前記アイランドの主面に固着された半導体素子と、
前記半導体素子と接続されて一端が外部に露出するリードと、
前記アイランド、前記半導体素子および前記リードの一部を被覆する封止樹脂と、
連結部を介して前記アイランドと連続して前記封止樹脂の側面から外部に露出するタブと、
前記連結部の両側辺および前記アイランド周囲を連続して厚み方向に突出させた突出部と、
前記連結部の両側辺に設けられた前記突出部に到達するように前記連結部の上面を窪ませた段差部と、を備えたことを特徴とする半導体装置。 The island,
A semiconductor element fixed to the main surface of the island through a bonding material flowing out by heat;
A lead connected to the semiconductor element and having one end exposed to the outside;
A sealing resin that covers a part of the island, the semiconductor element, and the lead;
A tab exposed to the outside from the side surface of the sealing resin continuously with the island through a connecting portion;
Protruding portions that continuously protrude in the thickness direction from both sides of the connecting portion and the periphery of the island;
A semiconductor device, comprising: a stepped portion in which an upper surface of the connecting portion is recessed so as to reach the protruding portions provided on both sides of the connecting portion. 前記段差部は、複数の段差形状を備えることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the step portion has a plurality of step shapes. 前記接合材は、鉛半田であることを特徴とする請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein the bonding material is lead solder. 前記接合材の一部は前記段差部に貯留されることを特徴とする請求項３記載の半導体装置。   The semiconductor device according to claim 3, wherein a part of the bonding material is stored in the step portion. 前記段差部の側面の一部は傾斜面であることを特徴とする請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein a part of the side surface of the step portion is an inclined surface. アイランドと、
ロウ材を介して前記アイランドの主面に固着された半導体素子と、
前記半導体素子と接続されて一端が外部に露出するリードと、
前記リードが設けられた一側辺と対向する他方の側辺に一体で延在し、前記アイランドの幅よりも狭い少なくとも１本の連結部と、
前記連結部と一体で前記側辺と平行に延在されるタブと、
前記アイランド、前記半導体素子、前記リードの一部および前記連結部の少なくとも一部を覆う封止樹脂と、を有し、
前記連結部の両側辺には、上方に向かって突出部が設けられると共に、２つの前記突出部の間には、前記突出部よりも下方に位置する表面部があり、
前記連結部が設けられた所の近傍に位置する半導体素子の周囲には、前記ロウ材がはみ出して設けられ、
前記はみ出したロウ材の流れ出し流路と成る前記表面部および前記表面部と突出部の境界近傍には、前記表面部から前記境界を越えて前記突出部に到る凹み部が設けられることを特徴とした半導体装置。 The island,
A semiconductor element fixed to the main surface of the island via a brazing material;
A lead connected to the semiconductor element and having one end exposed to the outside;
Extending integrally with the other side opposite the one side where the lead is provided, and at least one connecting portion narrower than the width of the island;
A tab that is integral with the connecting portion and extends parallel to the side;
A sealing resin that covers the island, the semiconductor element, a part of the lead, and at least a part of the connecting portion;
On both sides of the connecting part, a protruding part is provided upward, and between the two protruding parts, there is a surface part positioned below the protruding part,
Around the semiconductor element located in the vicinity of the place where the connecting portion is provided, the brazing material protrudes and is provided.
In the vicinity of a boundary between the surface portion and the surface portion and the protruding portion, which is the flow-out flow path of the protruding brazing material, there is provided a recessed portion extending from the surface portion to the protruding portion beyond the boundary. A semiconductor device. 前記凹み部は、
両側に位置する前記境界を越えて前記突出部に到る第１の凹み部と、
前記連結部の幅よりも狭く前記連結部の延在方向に設けられた第２の凹み部と、を有することを特徴とした請求項６に記載の半導体装置。 The recess is
A first recess that reaches the protrusion beyond the boundary located on both sides;
The semiconductor device according to claim 6, further comprising: a second recess portion that is narrower than a width of the connecting portion and provided in an extending direction of the connecting portion. 連結部を介してタブが連続するアイランドと前記アイランドに一端が接近するリードとを含み、前記アイランドおよび前記連結部の周辺部を厚み方向に突出させた突出部が設けられたリードフレームを用意する工程と、
前記連結部の両端に設けられた前記突出部に到達するように、前記連結部の上面を窪ませて段差部を設ける工程と、
固着材を介して前記アイランドの上面に半導体素子を固着し、前記半導体素子と前記リードとを接続する工程と、
前記半導体素子、前記アイランドおよび前記リードを封止樹脂により被覆する工程と、を備えたことを特徴とする半導体装置の製造方法。 A lead frame is provided that includes an island in which tabs are connected via a connecting portion and a lead having one end approaching the island, and a protruding portion in which a peripheral portion of the island and the connecting portion protrudes in a thickness direction. Process,
A step of providing a stepped portion by recessing the upper surface of the connecting portion so as to reach the protruding portions provided at both ends of the connecting portion;
Fixing a semiconductor element to the upper surface of the island through a fixing material, and connecting the semiconductor element and the lead;
And a step of coating the semiconductor element, the island and the lead with a sealing resin. 前記段差部を設ける工程では、
第１金型により前記連結部を上面からプレスすることにより第１段差部を設け、
前記第１金型よりも幅が広い第２金型により、前記第１段差部の周辺部の前記連結部の上面をプレスすることで、前記第１段差部の側辺を内側に傾く傾斜面とすることを特徴とする請求項８記載の半導体装置の製造方法。 In the step of providing the step portion,
A first step portion is provided by pressing the connecting portion from above with a first mold,
An inclined surface that inclines the side of the first stepped portion inward by pressing the upper surface of the connecting portion at the periphery of the first stepped portion with a second die that is wider than the first die. The method of manufacturing a semiconductor device according to claim 8. 前記半導体素子を固着する工程では、
鉛半田を用いて前記半導体素子を前記アイランドの上面に固着することを特徴とする請求項９記載の半導体装置の製造方法。


In the step of fixing the semiconductor element,
The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor element is fixed to the upper surface of the island using lead solder.


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JP2013016709A (en) * 2011-07-05 2013-01-24 Toshiba Corp Semiconductor device
KR101481368B1 (en) 2012-10-26 2015-01-14 아사히 가세이 일렉트로닉스 가부시끼가이샤 Magnetic sensor
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Publication number Priority date Publication date Assignee Title
JP2013016709A (en) * 2011-07-05 2013-01-24 Toshiba Corp Semiconductor device
KR101481368B1 (en) 2012-10-26 2015-01-14 아사히 가세이 일렉트로닉스 가부시끼가이샤 Magnetic sensor
KR101543970B1 (en) 2012-10-26 2015-08-11 아사히 가세이 일렉트로닉스 가부시끼가이샤 Magnetic sensor
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same
JP2018056309A (en) * 2016-09-28 2018-04-05 エイブリック株式会社 Semiconductor device
JP2018113359A (en) * 2017-01-12 2018-07-19 ローム株式会社 Semiconductor device
JP2019062245A (en) * 2019-01-29 2019-04-18 ローム株式会社 Semiconductor device

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