JPS60241140A - Address tracing device of microprogram - Google Patents

Abstract

PURPOSE:To attain collection of effective trace information by deciding optionally the trace timing with the address of microprogram and also designating optionally the write inhibition in a loop. CONSTITUTION:Two bits of a tracing control memory 3 consists of an indication bit for internal state of a control circuit 5 and an indication bit for storage of address to the circuit 5. The circuit 5 has a state (control state) of ''0'' or ''1'' and gives an indication to a tracing memory 6 for storage of address according to said two bits and the control state of the time point. The circuit 5 also changes the control state. The memory 6 stores a microprogram address to a temporary storage register 4 according to a storage indicating signal given from the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram address tracing device.

(Prior art) In a conventional microprogram address trace device, the trace memory capacity is limited, and the write timing occurs every clock, every fixed time, every instruction, every event, or every external input signal. Ta. Therefore, if a loop occurs in the program, or if there are many trace timings between one trace-required address and the next trace-required address, the necessary trace information will be lost. (Problems to be solved by the invention) The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and its purpose is to arbitrarily determine the trace timing by the address of a microprogram and to prevent writing in a loop. An object of the present invention is to provide a microprogram address tracing device capable of collecting effective trace information by arbitrarily specifying it.

(Summary of the Invention) The present invention allows arbitrary addresses to be stored in the trace memory as trace information in the microprogram address trace of a control device that performs microprogram control using memory, and furthermore, the specified addresses are continuous. If this occurs, tracing is prohibited from the second time onwards.

Its features include a trace memory for storing a microprogram address, storage instruction means for instructing whether or not to store the microprogram address in the trace memory, and a state for instructing the trace state. an instruction means, a control state management means for managing a control state as to whether or not the current microprogram address is in a traceable state; and means for giving a write instruction to the memory for use.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a microprogram address tracing device according to an embodiment of the present invention. In the figure, 1 is a microprogram address generation circuit that generates the current microprogram address and the next microprogram address of the program, 2 is a control memory that stores the next microprogram address, control data, etc. at the current microprogram address, and 3 is a control memory that stores the next microprogram address, control data, etc. A trace control memory consisting of a 2-bit wide ROM or RAM that instructs whether or not to store the microprogram address in the trace memory at a certain microprogram address; 4 is a temporary storage register for temporarily storing the microaddress; , 5 is a trace control circuit that instructs the trace memory to store an address, and 6 is a trace memory that stores trace information. Note that the tracing control memory 3 may be configured with ROM and uniquely determined, or configured with RAM so that it can be freely rewritten, so that it can be configured in accordance with instructions from the maintenance device or from the host device. It may be rewritten arbitrarily according to instructions. Further, the temporary storage register 4 is a circuit that latches the microprogram address, and is not necessary if the microprogram address can be normally stored in the trace memory 6 before the microprogram address changes.

Two bits of the trace control memory 3 are control circuit internal state indication bits (hereinafter referred to as state bits).
and an address storage instruction bit to the control circuit 5 (hereinafter referred to as storage bit). The control circuit 5 has O', 1. ' (hereinafter referred to as the control state), it instructs the trace memory 6 to store an address based on the above two bits and the control state at that time, and also controls the control state. change. The trace memory 6 stores the microprogram address using the temporary storage register 4 based on a storage instruction signal from the control circuit 5. Table 1 shows trace control memory 2.
The relationship between bits, control states, and storage instruction signals from the control circuit 5 to the trace memory 6 is shown.

TCM 2 bits of control memory 3 for tracing in Table 1
When expressed as (status bit, storage bit), TCM
(0, O) does not send a storage instruction signal and does not change the control state. TCM (0.

1) sends out a storage instruction signal that is unrelated to the control state, but
No change is made to the control state. TCM (1,0) does not send out a storage instruction signal and sets the control state to O. TCM
(1,1) sends out a storage instruction signal and inverts the control state when the control state is 0', but does nothing when the control state is 1.

For addresses that need to be traced unconditionally, the trace control memory 3 for that address is transferred to the TCM (
0,1). When determining whether or not to trace based on the control state, use TCM (1, 1). TCM (
1, 1) is used when the same address repeatedly issues a trace request due to a loop, etc., and the first time is traced and the second and subsequent times are not traced. First, when the control state O passes the address of TCM (1,1), a storage instruction signal is sent, the address is stored in the trace memory 6, and the control state is inverted to 1. The next time the same address is passed, the control state is 1, so the storage instruction signal is not sent, and the control state remains 1'. No matter how many times the same address is passed thereafter, as long as the control state is 1, it will not be traced.

FIG. 2 is a microprogram flowchart showing the operation of this embodiment. In this flow, if you want to know only the control flow, you can consider setting the status bit and storage bit as shown in the figure, for example. For example, if all branches are not taken, the program flows as shown in Table 2, and the data shown in Table 3 is stored in the trace memory 6.

(The following is a margin) Table 2 Table 3 Furthermore, when the program flows as shown in Table 4, the data shown in Table 5 is stored in the trace memory 6.

(Rejection margin) In Table 4, Table 5, and Figure 2, address n+11. The loop at n+19 is designed to be traced only once no matter how many times it loops, but for example, if you want to trace the number of times address n+19 is looped, set the trace control memory at address n+19 to TCM (0゜l). Bye.

As described above, in this embodiment, an arbitrary address can be traced, and it is also possible to trace only once in a loop, and necessary information can be stored effectively and in a small memory capacity.

(Effects of the Invention) As described above in detail, according to the present invention, the trace timing can be arbitrarily determined by the address of the microprogram, and write prohibition in a loop can also be arbitrarily specified. Therefore, there is an advantage that necessary information can be stored effectively and in a small memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of one embodiment of the present invention. 1-m-Microprogram address generation circuit. 2-m-control memory, 3--control memory for trace, 4--11 temporary storage register, 5--) race control circuit, 6-- memory for trace. Book 1 illustration

Claims (1)

[Claims] a trace memory for storing a microprogram address; storage instruction means for instructing whether or not to store the microprogram address in the trace memory; and a state instruction means for instructing a trace state; a control state management means for managing a control state as to whether a microprogram address is in a traceable state; and a control state management means for instructing a write to the trace memory when the control state is in a traceable state and storage of the microprogram address is instructed. A microprogram address tracing device characterized in that it has means for giving.