JPS59173822A - Bus monitoring system - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines for bus monitoring by recording a bus operation starting command and information on a bus which includes information on an address data common line. CONSTITUTION:The bus monitoring system is constituted of bus requesting sources 1-8, main memory 9, bus common control part 10, bus monitor 11, and a bus 12. The bus 12 includes the address data common line carrying an address and data with time division. The bus monitor 11 includes a tracer memory and records the bus operation starting indication and the information on the bus 12 which includes the information on the address data common line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus monitor system, and particularly to a bus monitor system to which a plurality of bus request sources are connected and which includes an address/data common line.

As is well known, a bus monitor is a tracer that records logical state transitions such as menus, bus permissions, addresses, data, and error information in chronological order to analyze performance problems and abnormal operations related to bus operations. Memory is the main component.

Generally, such bus monitors are installed within the unit that performs the main control of bus operations, but due to space constraints, there are cases where they are connected to the bus as an independent bus monitor unit, or where space and bus Due to restrictions on the electrical characteristics of the signal, it may be accommodated in one of the bus request sources.

In any case, as described above, the bus monitor records a large amount of information, so it is desirable to reduce the number of input/output signal lines.

A conventional bus monitor system of this type includes a bus common control unit that provides bus permission and bus operation start instructions to bus requests from each bus request source based on predetermined priorities;
a bus sequence circuit for each of the bus request sources, which outputs the address and data to a predetermined position on the address/data common line at a predetermined timing with the bus operation start instruction as a starting point when the bus permission is granted; and a tracer memory for recording information on the bus including bus permission, the bus operation start instruction, and information on the address/data shared line. The bus grant is propagated from the bus common control unit through signal lines connected to each bus request source in a star or decimal chain configuration.

In such a conventional configuration, the tracer memory identifies and records the bus request source that received the bus grant. This has the disadvantage that the number of bus monitor signal lines increases. In addition, when bus permissions are propagated through signal lines connected in a decimal chain, it is not possible to identify the bus request source that received the bus permission by the bus permission, so each bus request source is individually assigned to the tracer memory. It is necessary to be able to supply identification signals for the bus monitor, and as with the star connection, there is a drawback that the number of signal lines for the bus monitor increases.

An object of the present invention is to provide a bus monitor system in which the number of signal lines to the bus monitor is reduced.

The system of the present invention is a node monitor system in which a plurality of bus request sources are connected and includes an address/data common line, and includes an identification circuit for each of the bus request sources that holds its own identification information; a bus common control unit that provides bus permission based on a predetermined priority order and a bus operation start instruction in response to a bus request from each bus request source; a path sequence circuit for each of the bus request sources that outputs to a predetermined position on the address/data common line and at a predetermined timing with the bus operation start instruction as a starting point; the bus operation start instruction and the address/data; A tracer memory for recording information on the bus including information on the shared line is provided.

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing one embodiment of the present invention, this embodiment shows 8
8, a main memory 9, a bus common control section 10, a bus monitor 11, and a bus 12. Bus request source 1, 2...
Specifically, 8 may be at the level of an execution processor (EPS), an input/output processor (IOP), a mass storage processor (M8P), or a magnetic disk adapter, printer adapter, display controller, etc. It may be at the level of bus 1
2 includes an address/data common line that conveys addresses (24 pits) and data (32 bits) in a time-division manner.

FIG. 2 shows the bus request sources 1, 2, shown in FIG.・・・・・・
・A partial detailed diagram common to each of the 8 is shown, and shows the ID circuit 20, address register 21, four write registers 22, 23, 24 and 25, multiplexer 26, bus sequencer 27, driver 28, and , receiver 29, and four read registers 2 A l
2 B, 2 C and 2D. The address register 21 can hold data to which data is to be transferred. The driver 28 outputs the output of the multiplexer 26 to the address/data shared line of the bus 12. The receiver 29 receives read data one byte at a time from the bus 12 and sequentially holds it in each of the read registers 2A, 2B, 2C and 2D.

FIG. 3 is a partial detailed diagram of the bus monitor 110 shown in FIG.
As a circuit, the receiver 30 receives input from the bus 12.

FIG. 4 shows a partial detailed diagram (for 1 bit) of the IDEC circuit 200 in FIG.
1 and two resistors 42 and 43. In response to turning on or off the switch 41, the driver 40
v or oV, and identification information of eight bus request sources 1, 2, . . . 8 can be coded in advance using three such circuits.

In FIG. 1, when at least one of the bus request sources 1, 2, . . . 8 wishes to use the bus 12, it outputs a bus request R to the bus common control circuit 10.

When the bus 12 becomes usable, the bus common control circuit 1o sends it to the bus request source if there is only one bus request R, or to a predetermined priority order if there are multiple bus requests R. Bus permission A is granted to only one bus request source determined based on the above information. Based on the priority order, the requester will be granted permission to proceed (once the requester is placed in advance) (once the requester has completed the request, the requester will be granted permission in order based on the 11th priority).

The bus common control circuit 10 also outputs a nox operation start instruction signal K to the bus 12, and in response to this bus operation start instruction signal K, the bus requestor who has been given the nox permission first responds to the bus operation start instruction signal K.
A mode instruction signal M is outputted onto the bus 12 and bus operation is started. The modes are divided according to the write operation and read operation, the number of data transfer bytes (1 to 4), and the like.

The bus sequencer 27 shown in FIG. 2 sequentially outputs signals for switching the inputs of the multiplexer 26 in response to the mode instruction signal MK. The ID circuit 20 and the address register 21 simultaneously operate regardless of the mode.
Dryno (output to 28. Write register 22, 2
3. 24 and 25 correspond to the number of data transfer bytes during a write operation) and are output to the driver 28, and 2 read registers, 2 B l 20 and 2D correspond to the number of data transfer bytes during a read operation. Then, read data is sequentially received from the receiver 29.

The bus permission A, bus operation start instruction signal, mode instruction signal M, address, data, etc. appearing on the bus 12 are
Input to the receiver 30 in the figure, write control circuit 33
is written and recorded at the address of the tracer memory 32 specified by the tracer address circuit 34 via the register 31 under the control of the tracer address circuit 34. These pieces of information written in the tracer memory 32 are read by a readout circuit (not shown).
The information is read out at a timely manner and used for performance analysis and abnormal operation analysis regarding bus operations.

FIG. 5 shows a waveform diagram when one of the bus request sources 1 to 8 reads out the main memory 9, and FIG. 6 shows the information recorded in the tracer memory 32 at this time in chronological order. It is shown in The information on the address/data common line is between timings t1 and t2, the identification information of the bus request source whose bus permission A was input, and the address of the main memory 9, and between timings t4 and t15, the main memory 9 This is the data read from.

In this embodiment, the address and data carried by the address/data common line in a time-division manner have a 24-bit configuration and a 32-bit configuration, respectively, and the difference in the number of bits between the two is used to express identification information. However, the present invention is not limited thereto.

In other words, since the number of address bits is generally smaller than the number of data bits, there are many cases where the address and identification information are transmitted on the address/data common line at the same time, as in the above embodiment. If the relationship between the number of bits and the data is somewhat reversed, the data and the identification information may be mixed. In addition, regardless of the relationship between the number of bits between the address and data, identification information can be stored in the address and data during a time period when the address and data do not overlap.
It may also be sent out on the data common line.

According to the present invention, by employing the above-described configuration, there is no need for the tracer memory to receive bus permission via a dedicated line, so the number of signal lines of the bus monitor can be reduced.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIGS. 2, 3, and 4 are detailed views of the embodiment, and FIGS. 5 and 6 are diagrams for explaining the embodiment. be. 1.2-8...Bus request source, 9...Main memory, 10...Bus common control unit, 11.
...Bus monitor, 12...Bus, 20.
...Ide circuit, 21...Address register, 22.23.24.25...Write register, 26...Multiplexer, 27...
...Bus sequencer, 28140・river...driver,
29.30...Receiver, 2A, 2B,
2C, 2D...read register, 31...
...Register, 32...Tracer memory, 3
3...Write control circuit, 34...Tracer address circuit, 41...Switch, 42
, 43...Resistor, C...Clock,
R: Bus request, A: Bus permission, M
...Mode instruction signal, D...Data on the address/data shared line, S...Strobe, K...Bus operation start instruction signal, 0... ...
- Termination instruction signal. Mata 2] N' Enemy 1 Goryo 31 Kaya 4 times

Claims (1)

[Scope of Claims] A bus monitor system for a bus to which a plurality of bus request sources are connected and includes an address/data shared line, comprising: an identification circuit for each of the bus request sources that retains its own identification information; a bus common control unit that gives a bus permission and a bus operation start instruction based on a predetermined priority order in response to an original bus request; a path sequence circuit for each bus request source that outputs the bus operation start instruction and information on the address-data common line to a predetermined position and at a predetermined timing starting from the bus operation start instruction; A bus monitor system 0 characterized in that it is provided with a tracer sled for recording information on the bus including