JPH06119468A - Microcomputer - Google Patents

Abstract

PURPOSE:To test the function of an interruption controller without depending on any peripheral device concerning the microcomputer incorporating the interruption controller. CONSTITUTION:An interruption controller 14 is provided with at least storage device masters 6 and 11 for receiving and holding interruption requests from plural peripheral devices 15 and 16 and enabling write from a central processing unit 1 through a prescribed internal bus, storage device slaves 7 and 12 for receiving and holding these outputs and enabling write 7 read from the central processing unit 1 through the internal bus, and read/write controllers 4 and 9 for controlling read/write to the storage device masters and storage device slaves. Then, the function of the interruption controller 14 is tested without depending on any interruption request due to the peripheral devices 15 and 16 through a specified interruption control signal 109 inputted from the outside to the read/write controllers 4 and 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer for improving the function test of an interrupt controller.

[0002]

2. Description of the Related Art In a microcomputer including a central processing unit for executing instructions and accessing a storage device such as a memory, and a plurality of peripheral devices such as a timer, a serial interface, and an analog-digital converter, An interrupt control device for controlling an interrupt request from the device is provided. The interrupt control device selects one interrupt request from a plurality of interrupt requests generated from peripheral devices according to the priority order set for each interrupt request, and requests execution of interrupt processing for the selected interrupt request. It is a device having a function of transmitting to the central processing unit.

The structure of a conventional microcomputer having a central processing unit, a peripheral device and an interrupt control device will be described with reference to the block diagram of the microcomputer shown in FIG. 5, focusing on the interrupt control device.

As shown in FIG. 5, the microcomputer is composed of a central processing unit 1 and an interrupt control device 14 corresponding to the peripheral devices 15 and 16. The interrupt control device 14 holds the interrupt request flag 8 for holding the occurrence of the interrupt request signal 120 output from the peripheral device 15, and the existence of the interrupt request signal 129 output from the peripheral device 16. Of the interrupt request flag 8 in the interrupt control device 14 and the interrupt request signal 129 output from the peripheral device 16 The interrupt request flag 13 for holding the presence / absence of the occurrence, the address information on the internal address bus 101 output from the central processing unit 1, and the interrupt request flag 8 in the interrupt control unit 14 are assigned to the interrupt request flag 13. Address decoder 2 for determining whether or not it matches the received address, and a storage device in the interrupt request flag 8. State and interrupt the slave output signal 121 is the output of the slave 7 request flag 1
Depending on the state of the slave output signal 130, which is the output of the storage device slave 12 in FIG. 3, an interrupt processing execution request is sent via the interrupt processing execution request signal 106 to the central processing unit 1.
And an arbitration device 3 for outputting to.

Next, the address decoder 2 in the interrupt controller 14 will be described. The address decoder 2 outputs a select signal 107 used to access the storage device slave 7 in the interrupt request flag 8 and a select signal 108 used to access the storage device slave 12 in the interrupt request flag 13. To generate. When the address information on the internal address bus 101 output from the central processing unit 1 matches the address assigned to the interrupt request flag 8, the select signal 107 is set to "1" and the internal address bus 101 If the address information of the internal address bus 101 matches the address assigned to the interrupt request flag 13, the select signal 108 is set to “1” and the address information on the internal address bus 101 is assigned to the interrupt request flags 8 and 13. If the selected address is neither one of the selected addresses 107 and 10
Both 8 output "0".

Next, the arbitration device 3 in the interrupt control device 14
Will be described. The arbitration device 3 uses the slave output signal 1
Depending on the states of 21 and 130, whether the interrupt processing execution request signal 106 is set to "1" or "0" is set. That is, when at least one of the slave output signals 121 and 130 is “1”, one of them is selected according to the set priority order and the interrupt processing execution request signal 106 is set to “1”, and at the same time, It holds whether the slave output signal 121 or the slave output signal 121 was selected. In the arbitration device 3, the central processing unit 1 uses the interrupt processing execution request signal 1
When the interrupt processing reception signal 105 indicating that 06 has been received is generated, the slave reset signal 110 or the slave reset signal 112 is generated. When the slave output signal 121 is selected and the interrupt processing execution request signal 106 becomes "1", when the interrupt processing reception signal 105 becomes "1", the slave reset signal 110 becomes "1" and the slave reset The signal 112 becomes “0”. Conversely, when the slave output signal 130 is selected and the interrupt processing execution request signal 106 becomes "1",
When the interrupt processing reception signal 105 becomes "1", the slave reset signal 112 becomes "1" and the slave reset signal 110 becomes "0". As a result, the storage device slave in the interrupt request flag corresponding to the interrupt processing executed in the central processing unit 1 becomes "0". Also, the arbitration device 3 sets the interrupt processing execution request signal 106 to “0” when the interrupt processing reception signal 105 becomes “1”.

Next, the interrupt request flags 8 and 13 will be described. The interrupt request flag 8 is composed of two storage devices, a storage device master 6 and a storage device slave 7, and a read / write control device 4 that controls access from the central processing unit 1 to the storage device slave 7. The interrupt request flag 13 is composed of two storage devices, a storage device master 11 and a storage device slave 12, and a read / write control device 9 that controls access from the central processing unit 1 to the storage device 1 slave 12. ,
It is structurally the same as the interrupt request flag 8.

Next, the structure of the interrupt request flags 8 and 13 will be described. Since the interrupt request flag 13 has the same structure as the interrupt request flag 8, detailed description will be omitted and the interrupt request flag 8 will be described in detail.

Storage device master 6 in interrupt request flag 8
Is an interrupt request signal 120 output from the peripheral device 15.
Becomes "1" when it becomes "1", and becomes "0" when the master reset signal 119 output from the storage device slave 7 becomes "0". When both the interrupt request signal 120 and the master reset signal 119 are "0", the previous value is held. The value of the storage device master 6 is the master output signal 1
It is output as 18.

The storage device slave 7 in the interrupt request flag 8 is connected to the read / write control device 4 in the interrupt request flag 8.
When the transfer permission signal 115 output from the memory device is "1" and the master output signal 118 which is the output signal of the storage device master 6 is "1", "1" is held and the transfer permission signal 1
15 is "0" or the master output signal 118 is "0"
In case of, the held value is not changed. Further, the storage device slave 7 outputs the held value to the internal data bus 104 while the value of the slave read signal 114 output from the read / write control device 4 is “1”. The storage device slave 7 reads and holds the value on the internal data bus 104 when the value of the slave write signal 113 output from the read / write control device 4 is “1”. When the storage device slave 7 holds “1”, the storage device slave 7 outputs “1” to the master reset signal 119. The storage device slave 7 becomes "0" when the slave reset signal 110 output from the arbitration device 3 is "1", and holds the previous value when the slave reset signal 110 is "0".

Next, the read / write control device 4 in the interrupt request flag 8 will be described. When the value of the select signal 107 which is the output signal of the address decoder 2 is “1” and the value of the read signal 102 which is the output signal from the central processing unit 1 is “1”, the read / write control device 4 "1" is output to the slave read signal 114, the value of the select signal 107 which is the output signal of the address decoder 2 is "1", and the value of the write signal 103 which is the output signal from the central processing unit 1 is "1". When it is "1", "1" is output to the slave write signal 113. Further, the read / write control device 4 outputs "0" to the transfer permission signal 115 when outputting "1" to the slave read signal 114 or the slave write signal 113, and otherwise outputs "1". Output. That is, the transfer permission signal 115 output from the read / write control device 4 becomes “1” when the central processing unit 1 is not accessing the storage device slave 7 in the interrupt request flag 8 and “0” when it is accessing. "It becomes.

Next, the operation of the microcomputer itself will be described focusing on the interrupt controller 14.

First, after an interrupt request is generated in the peripheral device 15 and the interrupt request signal 120 becomes "1",
The operation of the microcomputer until the central processing unit 1 accepts the interrupt processing will be described. It should be noted that after an interrupt request is generated in the peripheral device 16 and the interrupt request signal 129 becomes "1", the central processing unit 1
The operation of the microcomputer until the interrupt processing is accepted is the same as that of the peripheral device 15 except for the device that generates the interrupt request signal, and therefore the description thereof is omitted. Further, in explaining the operation, FIGS. 6 (a), (b), (c), (d),
(E), (f), (g), (h), (i) and (j)
Use the timing diagram shown in.

In FIG. 6, at time T ₃₁ , an interrupt request is generated in the peripheral device 15, and the interrupt request signal 120 becomes "1". At T ₃₂ , since the interrupt request signal 120 becomes “1”, “1” is held in the storage device master 6 in the interrupt request flag 8 and the master output signal 118 also becomes “1”. At T ₃₃ , since the transfer permission signal 115 output from the read / write control device 4 is “1” and the master output signal 118 is “1”, “1” is held in the storage device slave 7. At T ₃₄ , since the slave output signal 121 is “1”, the arbitration device 3 selects the slave output signal 121,
“1” is output to the interrupt process execution request signal 106. Further, since the master reset signal 119 becomes "1", the memory device master 6 (see FIG. 6B) becomes "0".

During the period from T ₃₄ to T ₃₅ , the central processing unit 1 detects that the interrupt processing execution request signal 106 is "1", and when executing the interrupt processing, the interrupt processing reception signal 105 is set to "1". Set to 1 ”. In T ₃₅ later, the central processing unit 1 is running interrupt processing.
At T ₃₅ , the interrupt processing reception signal 105 becomes “1”, and since the arbitration device 3 selects the slave output signal 121, the slave reset signal 110 output from the arbitration device 3 becomes “1”. At T ₃₆ , since the slave reset signal 110 is “1”, the storage device slave 7 (see FIG. 6E) becomes “0”. Since the storage device slave 7 has become “0”, the slave output signal 121 and the master reset signal 119 become “0”.

The above operation is the operation of the microcomputer from when the interrupt request is generated in the peripheral device 15 and the interrupt request signal 120 becomes "1" until the interrupt processing is accepted in the central processing unit 1.

Next, the operation when the central processing unit 1 accesses the storage device slave 7 in the interrupt request flag 8 will be described. Access to the storage device slave 7,
Since the access to the storage device slave 12 operates in the same manner except that the addresses assigned to the interrupt request flags 8 and 13 are different, the storage device slave 7
The operation of accessing the storage device slave 12 will be described, and the description of the access to the storage device slave 12 will be omitted.

A write operation to the storage device slave 7 in the interrupt request flag 8 will be described with reference to FIGS.
This will be described with reference to the timing charts shown in (c), (d), (e), (f) and (g).

At T ₄₁ , the central processing unit 1 outputs the address assigned to the interrupt request flag 8 to the internal address bus 101. The address of the interrupt request flag 8 is the address of the internal address bus 101 from T ₄₁ to T _44.
Output above. The address decoder 2 in the interrupt control device 14 outputs the address assigned to the interrupt request flag 8 in the interrupt control device 14 on the internal address bus 101, so that the select signal 107 is output from T ₄₁ to T _44. "1" is output to. During T ₄₂ to T _44, the write signal 103 output from the central processing unit 1 becomes “1”, and at the same time, write data is output to the internal data bus 104 output from the central processing unit 1. At T ₄₂ , since the write signal 103 is “1” and the select signal 107 is “1”, the read / write control device 4 in the interrupt request flag 8 changes the slave write signal 11
"1" is output to 3. Also, the slave write signal 11
Since 3 has become "1", the read / write control device 4 outputs "0" to the transfer permission signal 115. At _T43 , since the slave write signal 113 is "1", the storage device slave 7 takes in the write data on the internal data bus 104, and thereafter the storage device slave 7 holds the fetched data.

At T ₄₄ , the internal address bus 101
The address information above is not the address assigned to the interrupt request flag 8 in the interrupt controller 14. Further, the write signal 103 becomes "0", and the write operation to the storage device slave 7 in the interrupt request flag 8 of the interrupt control device 14 ends. Upon completion of the write operation, both the select signal 107 and the slave write signal 113 in the interrupt controller 14 become "0", and the transfer enable signal 1
15 becomes "1". Here, when the value held in the storage device slave 7 in the interrupt request flag 8 is "1", the storage device slave 7 in the interrupt request flag 8 is generated by the generation of the interrupt request signal 120 described above. "1" is set in the subsequent operation (T ₃₃ later in FIG. 6) and the same operation is continuously performed in the interrupt control device 14.

Next, the read operation to the storage device slave 7 in the interrupt request flag 8 will be described with reference to FIG.
(B), (c), (d), (e), (f) and (g)
This will be described with reference to the timing chart shown in FIG.

At T ₅₁ , the central processing unit 1 outputs the address assigned to the interrupt request flag 8 to the internal address bus 101. Address of the interrupt request flag 8, in the period from T ₅₁ to T _53, is outputted onto the internal address bus 101. Address decoder 2 interrupt control unit 14, since the address assigned to the interrupt request flag 8 of the interrupt control device 14 on the internal address bus 101 is output, between T ₄₁ of T _44,
“1” is output to the select signal 107.

From T ₅₂ to T ₅₃ , the read signal 102 output from the central processing unit 1 becomes "1". Since the read signal 102 is “1” and the select signal 107 is “1” at T ₅₂ , the read / write control device 4 in the interrupt request flag 8 determines that the slave read signal 114
"1" is output to. Also, the slave read signal 114
Has become "1", the read / write control device 4 outputs "0" to the transfer permission signal 115. The slave read 114, which is the output from the read / write control device 4, is "0".
Therefore, the transfer permission signal 115 becomes "1".

The above is the operation when the interrupt request of the interrupt controller occurs and the access operation from the central processing unit to the storage device slave in the interrupt request flag.

When performing a function test of the interrupt control device 14 in such a microcomputer, the storage device slaves 7 and 12 and the read / write control device 4 are used.
As for 9 and 9, the address decoder 2, and the arbitration device 3, a functional test can be performed by performing a write operation to the storage device slaves 7 and 12 in accordance with an instruction from the central processing unit 1. However, the storage device master 6
Nos. 11 and 11 have no means for operating from the central processing unit 1, so that in the peripheral devices 15 and 16, "1" is generated in the interrupt request signals 15 and 16.

[0026]

In the above-mentioned conventional microcomputer, when a function test of the interrupt control device is performed, it is necessary to generate an interrupt request from the peripheral device, and therefore the peripheral device generates an interrupt. However, there is a drawback that the procedure of the function test becomes complicated because the setting for performing the setting must be performed.

Further, depending on the peripheral device, it takes a very long time to generate an interrupt. For example, when an interrupt is generated due to overflow of a timer, it is only necessary to generate an interrupt for tens of thousands to several tens. It has a drawback that it takes one million clocks and the time required for the functional test becomes long.

In general, in a microcomputer, when trying to meet market demands, it is possible to expand the product series by changing only the peripheral devices without changing the central processing unit and interrupt control unit. It is normal. But,
In a conventional microcomputer, when the peripheral device is changed, the procedure for generating an interrupt request from the peripheral device changes depending on the peripheral, even though the interrupt controller itself has not changed. Has to be created for each microcomputer, which requires a lot of man-hours.

[0029]

According to the present invention, there is provided a microcomputer including a central processing unit and an interrupt control device corresponding to a plurality of peripheral devices. Is received and held, and a first storage device writable from the central processing unit and an output of the first storage device are received and held via a predetermined internal bus, and the internal storage A second storage device capable of writing / reading to / from the central processing unit via a bus, and a read / write control device performing a write / read control operation for the first and second storage devices. The peripheral device is configured to be provided at least in the interrupt control device, and through a specific interrupt control signal externally input to the read / write control device. Without depending on the interrupt request by, it is characterized in that it is possible to perform a functional test of the interrupt controller.

[0030]

1 is a block diagram of a first embodiment of the present invention.
Will be described with reference to the block diagram of FIG. This embodiment is composed of a central processing unit 1 and an interrupt control device 14 corresponding to the peripheral devices 15 and 16. Hereinafter, each device included in this embodiment will be described.

Since the central processing unit 1 and the peripheral devices 15 and 16 are the same devices as the conventional example, detailed description thereof will be omitted. The input terminal 50 is connected to the peripheral devices 15 and 16
1 is input when the values of the storage device masters 6 and 11 in the interrupt request flags 8 and 13 are set to "1" without generating the interrupt request signals 120 and 129 from "1", and "0" otherwise. Is entered. The interrupt control device 14 has an interrupt request flag 8 for holding the presence or absence of an interrupt request signal 120 from the peripheral device 15, and an interrupt request signal 12 from the peripheral device 16.
Interrupt request flag 13 for holding the occurrence of 9
And the address bus 101 output from the central processing unit 1.
An address decoder 2 for determining whether or not the above address information indicates that the interrupt request flag 8 in the interrupt control device 14 matches the address assigned to the interrupt request flag 13, and a storage device in the interrupt request flag 8. Slave 7
Of the slave output signal 121 that is the output of the interrupt request and the state of the slave output signal 130 that is the output of the storage device slave 12 in the interrupt request flag 13 It has an arbitration device 3 for outputting to the central processing unit 1. Since the address decoder 2 and the arbitration device 3 are the same as those in the conventional example, detailed description thereof will be omitted.

The interrupt request flag 8 indicates that the storage device master 6
And a storage device slave 7, two storage devices, an access from the central processing unit 1 to the storage device slave 7, and a read / write for controlling a master set signal 116 for setting "1" in the storage device master 6. It is constituted by the control device 4. The interrupt request flag 13 also has the same structure. Two storage devices, a storage device master 11 and a storage device slave 12, access from the central processing unit 1 to the storage device slave 12, and “1” in the storage device master 11. The read / write control device 9 controls the master set signal 125 for setting "".

Next, the interrupt request flag 8 and the interrupt request flag 13 will be described. The interrupt request flag 13
Has the same configuration as the interrupt request flag 8, a detailed description of the interrupt request flag 13 will be omitted.

Storage device master 6 in interrupt request flag 8
Becomes "1" when the OR gate output signal 117 is "1" and becomes "0" when the master reset signal 119 which is the output from the storage device slave 7 is "1", and the OR gate output signal 117 becomes When it is "0" and the master reset signal 119 is "0", the previous value is held. OR
The gate 5 outputs "1" when the interrupt request signal 120 is "1" or the master set signal 116 output from the read / write control device 4 is "1", and the interrupt request signal 120 and the master set signal 116 are When both are "0", "0" is output. In addition, the value of the storage device master 6 is
The master output signal 118 is output to the storage device slave 7. Since the storage device slave 7 is the same as the conventional example, its description is omitted.

Next, the read / write control device 4 in the interrupt request flag 8 will be described.

In the read / write control device 4, the value of the select signal 107, which is the output signal of the address decoder 2, is "1", and the read signal 102, which is the output signal from the central processing unit 1, is "1". At the same time, “1” is output to the slave read signal 114, the value of the select signal 107 which is the output signal of the address decoder 2 is “1”, and the value of the write signal 103 which is the output signal from the central processing unit 1 is “1”. When it is "1" and the master test signal 109 input from the input terminal 50 is "0", "1" is output to the slave write signal 113, the value of the select signal 107 is "1", and the write signal 103 is Is 1 and the master test signal 109 input from the input terminal 50 is
When the value of is “1”, “1” is output to the master set signal 116. In other words, if the input terminal 50 is set to "1" and an attempt is made to write to the interrupt request flag 8, "1" is set in the storage device master 6 instead of writing to the storage device slave 7. Also, the input terminal 50
If "1" is set and an attempt is made to write to the interrupt request flag 13, "1" is set in the storage device master 11, not in the storage device slave 12. Furthermore, the read / write control device 4 outputs the transfer enable signal 115 while the slave read signal 114, the slave write signal 113, or the master set signal 116 is outputting “1”.
"0" is output to, and otherwise, "1" is output.

Next, the operation of the present embodiment will be described focusing on the interrupt controller 14. The operation when an interrupt request is generated and the operation when accessing the storage device slave in the interrupt request flag in the state where “0” is input to the input terminal 50 are the same as those in the conventional example, and therefore will be omitted. "1" is set to the storage device master in the interrupt request flag without generating an interrupt request from the peripheral device related to the invention.
2 (a), (b),
(C), (d), (e), (f), (g), (h),
This will be described with reference to the timing charts shown in (i), (j), (k), (l), (m), (n) and (p). Since the interrupt request flag 8 and the interrupt request flag 13 have the same configuration, here, the interrupt request flag 8 is generated without causing the storage device master 6 in the interrupt request flag 8 to generate an interrupt request from the peripheral device 15. Storage device master 6
The operation of setting "1" to will be described, and description of the interrupt request flag 13 will be omitted.

In FIG. 2, at T ₁₁ , "1" is input from the input terminal 50 and the master test signal 109 becomes "1". The central processing unit 1 has an internal address bus 1
The address assigned to the interrupt request flag 8 is output to 01. Address decoder 2 in interrupt controller 14
Detects that the address information on the internal address bus 101 is the same as the address assigned to the interrupt request flag 8 and outputs "1" to the select signal 107.

From T ₁₂ to T ₁₄ , the write signal 103 which is the output of the central processing unit 1 becomes "1". The write signal 103 is “1” and the master test signal 109 is “1”
And the select signal 107 is “1”,
The read / write control device 4 in the interrupt request flag 8 sets the master set signal 116 to "1". At this time, since the master test signal 109 is "1", the slave write signal 113 remains "0". Master set signal 1
Interrupt request flag 8 because 16 has become "1"
The OR gate output signal 117 of the OR gate 5 inside is "1".
Becomes Since the master set signal 116 becomes "1", the transfer permission signal 115 output from the read / write control device 4 in the interrupt request flag 8 becomes "0". At T ₁₃ , the OR of the OR gate 5 in the interrupt request flag 8
Since the gate output signal 117 is “1”, “1” is held in the storage device master 6. Since the memory device master 6 has become "1", the master output signal 118 becomes "1". At T ₁₄ , the write operation ends, and the address information assigned to the interrupt request flag 8 on the internal address bus 101 output from the central processing unit 1 is no longer output. Further, the write signal 103 output from the central processing unit 1 becomes "0". By this,
The select signal 107 in the interrupt controller 14 becomes "0", and the master set signal 116 in the interrupt request flag 8
Becomes "0". Since the master set signal 116 becomes "0", the OR gate output signal 117 which is the output of the OR gate 5 becomes "0", and the transfer permission signal 115 which is the output of the read / write control device 4 also becomes "0". Become.

At T ₁₅ , the master output signal 118, which is the output of the storage device master 6, is “1”, and the transfer permission signal 115, which is the output from the read / write control device 4, is “1”. “1” is held in the slave 7. By holding “1” in the storage device slave 7, both the slave output signal 121 and the master reset signal 119 become “1”. Slave output signal 121
Because it became the "1", the period T _16-from T _15, selects the slave output signal 121 at arbitrator within 3, in T _16, interrupt processing execution request signal 106 becomes "1". At T ₁₆ , the master reset signal 119 is “1”, so that the storage device master 6 (see FIG. 2G) in the interrupt request flag 8 becomes “0”.

Between T ₁₆ and T ₁₇ , the central processing unit 1
Detects that the interrupt processing execution request signal 106 is "1" and outputs "1" to the interrupt processing reception signal 105 when executing the interrupt processing. In the following T _17, the central processing unit 1 is running interrupt processing. T
_{At 17} , the interrupt processing reception signal 115 becomes "1" and the arbitration device 3 selects the slave output signal 121, so that the arbitration device 3 outputs "1" to the slave reset signal 110. At T ₁₈ , since the slave reset signal 110 is “1”, the storage device slave 7 in the interrupt request flag 8 becomes “0”. Since the storage device slave 7 becomes “0”, the slave output signal 121 and the master reset signal 119, which are the output signals of the storage device slave 7, become “0”. Interrupt processing receipt signal 1
The arbitration device 3 detects that 05 was “1” at T ₁₈ ,
_{At 19} , the arbitration device 3 outputs the interrupt processing execution request signal 10
Set 6 to "0".

By using the microcomputer having the above-mentioned configuration, the interrupt request is not generated from the peripheral device, but the write operation to the interrupt request flag is used to make the storage device master in the interrupt request flag. It becomes possible to set "1".

Next, a second embodiment of the present invention will be described with reference to the block diagram of FIG. In this embodiment, a control is performed to allocate a common address of each storage device master in the interrupt request flag and set "1" in the storage device master with the value of the data to be written to the assigned address. It is carried out. The present embodiment shown in FIG. 3 comprises a central processing unit 1 and an interrupt control unit 14 corresponding to the peripheral units 15 and 16. Since the central processing unit 1, the peripheral devices 15 and 16 and the input terminal 50 are the same as those in the first embodiment, detailed description will be omitted.

The interrupt control device 14 holds the presence or absence of the interrupt request signal 120 from the peripheral device 15 and holds the presence or absence of the interrupt request signal 129 from the interrupt request flag 16 for holding the presence or absence of the interrupt request signal 129. And whether the address information on the internal address bus 101 output from the central processing unit 1 matches the address assigned to the interrupt request flag 8 or the interrupt request flag 13 in the interrupt control device 14. Depending on the state of the address decoder 2 that determines, the state of the slave output signal 121 that is the output of the storage device slave 7 in the interrupt request flag 8 and the state of the slave output signal 130 that is the output of the storage device slave 12 in the interrupt request flag 13. , The interrupt processing execution request to the central processing unit 1 via the interrupt processing execution request signal 106. And a mediation device 3 that force.
Since the arbitration device 3 in the interrupt control device 14 is the same as the arbitration device shown in the conventional example, detailed description thereof will be omitted.

Next, the structure of the interrupt request flags 8 and 13 in the interrupt controller 14 will be described. The interrupt request flag 8 is for the storage device master 6 and the storage device slave 7.
Two storage devices, the access from the central processing unit 1 to the storage device slave 7, and the read / write control device 4 that controls the master set signal 116 for setting "1" in the storage device master 6. It is configured. The interrupt request flag 13 also has the same configuration, and has two storage devices, a storage device master 11 and a storage device slave 12, access from the central processing unit 1 to the storage device slave 12, and “1” for the storage device master 11. And a read / write control device 9 for controlling a master set signal 125 for setting.

Next, the interrupt request flags 8 and 13 are provided so that the storage device masters 6 and 11 in the interrupt request flags 8 and 13 can be accessed as one storage device.
An address different from the address assigned to is provided. By performing a write operation on the storage device masters 6 and 11 in the interrupt request flags 8 and 13 to an address assigned so that they can be accessed as a single storage device, the storage device masters 6 and 6 in the interrupt request flags 8 and 13 For 11, it is possible to set "1" without generating the interrupt request signals 120 and 129 from the peripheral devices 15 and 16. Since the storage device master 6, the storage device slave 7, the OR gate 5 and the storage device master 6 in the interrupt request flag 8 are the same as those in the first embodiment, detailed description will be omitted.

Next, the address decoder 2 in the interrupt controller 14 will be described. The address decoder 2 in the interrupt control device 14 operates while the address information transmitted from the central processing unit 1 via the internal address bus 101 matches the address assigned to the interrupt request flag 8 of the interrupt control device 14. , Select signal 107 is "1"
To Further, the select signal 108 is set to "1" while the address information on the internal address bus 101 matches the address assigned to the interrupt request flag 8.
The address information on the internal address bus 101 corresponds to the storage device masters 6 and 11 in the interrupt request flags 8 and 13.
Is set as one storage device and the address assigned so that it can be accessed matches the select signal 131.

Next, the read / write control device 4 in the interrupt request flag 8 will be described. In the read / write control device 4 in the interrupt request flag 8, the select signal 107 output from the address decoder 2 is "1", the select signal 107 output from the central processing unit 1 is "1", and Read signal 10 output from the central processing unit 1
While 2 is "1", the slave read signal 114 outputs "1", and the address decoder 2 outputs the write signal 1
While 03 is "1", the slave write signal 113 is "1".
, The select signal 131 output from the address decoder 2 is “1”, the write signal 103 output from the central processing unit 1 is “1”, and the write signal 103 is input from the input terminal 50. The master test signal 109 is "1" and the central processing unit 1 sends the data to the internal data bus 10
When the bit corresponding to the interrupt request flag 8 of the write data output via 4 is "1", "1" is output to the master set signal 116. Further, the read / write control device 4 outputs “1” to one of the slave read signal 114, the slave write signal 113, or the master set signal 116, which is the output from the read / write control device 4. While the transfer is in progress, "0" is output to the transfer permission signal 115, and otherwise "1" is output.

Next, the read / write control device 9 in the interrupt request flag 13 will be described. Interrupt request flag 1
The read / write control device 9 in the address decoder 3
Output of the select signal 108 is "1", and the read signal 102 output from the central processing unit 1 is "1".
During this period, the slave read signal 123 outputs "1", the select signal 108 output from the address decoder 2 is "1", and the write signal 103 output from the central processing unit 1 is "1". , "1" is output to the slave write signal 122, the select signal 131 output from the address decoder 2 is "1", the write signal 103 output from the central processing unit 1 is "1", and the input Master test signal 109 input from terminal 50 is "1"
, And when the bit corresponding to the interrupt request flag 13 of the write data output from the central processing unit 1 via the internal data bus 104 is "1", the master set signal 1
“1” is output to 25. The read / write control device 9 outputs the slave read signal 123 or the slave write signal 12 output from the read / write control device 9.
2 or "0" is output while the master set signal 125 is "1", and otherwise "1" is output.

Subsequently, in the present embodiment, the interrupt request signals 120 and 129 are not generated from the peripheral devices 15 and 16 to the memory device masters 6 and 11 in the interrupt request flags 8 and 13 of the interrupt controller 14, respectively. The operation of setting "1" to will be described. The operation of setting “1” to the storage device master 11 in the interrupt request flag 13 without generating the interrupt request signal 129 from the peripheral device 16 is as follows. Interrupt request signal 12 from peripheral device 15
This is the same operation as setting "1" without generating 0, and only the value of the write data output from the central processing unit 1 via the internal data bus 104 is different.
A detailed description of the operation of setting "1" to the storage device master 11 in the interrupt request flag 13 without generating the interrupt request signal 129 from the peripheral device 16 is omitted. The operation of setting "1" to the storage device master 6 in the interrupt request flag 8 without generating the interrupt request signal 120 from the peripheral device 15 is performed by the interrupt request flag 8
This is performed by performing a write operation to an address assigned so that the storage device masters 6 and 11 in the storage devices 13 and 13 can be accessed as one storage device.

4 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
This will be described with reference to the timing charts shown in (k), (l), (m), (n) and (q). In FIG. 4, T
_{In 21} , the “1” is input from the input terminal 50 and the master test signal 109 becomes “1”. An interrupt request is sent from the central processing unit 1 to the internal address bus 101 in order to perform a write operation to an address assigned so that the storage device masters 6 and 11 in the interrupt request flags 8 and 13 can be accessed as one storage device. The addresses assigned to the storage device masters 6 and 11 in the flags 8 and 13 so that they can be accessed as one storage device are output. The same address as the address assigned by the address decoder 2 in the interrupt controller 14 so that the address information on the internal address bus 101 can access the storage device masters 6 and 11 in the interrupt request flags 8 and 13 as one storage device. Is detected and "1" is output to the select signal 131.

At T ₂₂ , the write signal 103 output from the central processing unit 1 becomes “1”, and at the same time, write data is output from the central processing unit 1 via the internal data bus 104. This write data is interrupt request flag 8
The bit corresponding to is "1". Write signal 1
03 is "1", the master test signal 109 is "1", the select signal 131 is "1", and the bit corresponding to the interrupt request flag 8 of the write data is "1". The write controller 4 sets the master set signal 116 to "1". Since the master set signal 116 becomes "1", the O in the interrupt request flag 8
The R gate output signal 117 becomes "1". Since the master set signal 116 becomes "1", the transfer permission signal 115 which is the output of the read / write control device 4 becomes "0".

At T ₂₃ , the OR gate output signal 11
7 is "1", the storage device master 6 (see FIG. 4 (h)
“1” is held in (see). Since the memory device master 6 has become "1", the master output signal 118 becomes "1". At T ₂₄ , the write operation to the address assigned to the storage device masters 6 and 11 in the interrupt request flags 8 and 13 so that they can be accessed as one storage device is completed, and the central processing unit 1 outputs the result. The address information on the internal address bus 101 changes, and the write signal 103 output from the central processing unit 1 becomes "0". As a result, the select signal 131 becomes "0" and the master set signal 116 in the interrupt request flag 8 becomes "0". Since the master set signal 116 becomes “0”, the OR gate output signal 117
Becomes "0", and the transfer permission signal 115 output from the read / write control device 4 also becomes "0". At T ₂₅ , since the master output signal 118, which is the output of the storage device master 6, is “1” and the transfer permission signal 115 is “1”, the storage device slave 7 (see FIG. 4 (k)) shows “1”. "Is retained. By holding “1” in the storage device slave 7, both the slave output signal 121 and the master reset signal 119, which are the outputs of the storage device slave 7, become “1”.

[0054] By the slave output signal 121 becomes "1", the period of T ₂₆ from T _25, selects the slave output signal 121 at arbitrator within 3, in T _26, interrupt processing execution request signal 106 is " 1 ”. During the period from T ₂₆ to T ₂₇ , the central processing unit 1 outputs the interrupt processing execution request signal 1
When it is detected that 06 is "1" and the interrupt process is executed, "1" is output to the interrupt process reception signal 105. After T ₂₇ , the central processing unit 1 is executing interrupt processing. At T ₂₇ , the interrupt processing reception signal 105 becomes “1” and the arbitration device 3 selects the slave output signal 121, so that the slave reset signal 110 output from the arbitration device 3 becomes “1”. T
_{At 28} , since the slave reset signal 110 is “1”, the storage device slave 7 in the interrupt request flag 8
(See FIG. 4 (k)) becomes "0". Since the storage device slave 7 has become "0", the slave output signal 12
1 and the master reset signal 119 become "0". Further, at T ₂₈ , the arbitration device 3 detects that the interrupt processing reception signal 105 is “1”, and at T ₂₉ , the arbitration device 3 sets the interrupt processing execution request signal 106 to “0”.

The above operation is the interrupt request flags 8 and 1.
By performing a write operation on the addresses assigned to the storage device masters 6 and 11 in 3 so that they can be accessed as one storage device, the interrupt request signal 120
Is an operation of setting "1" to the storage device master 6 in the interrupt request flag 8 without changing the peripheral device 15 to "1". This operation is characterized by the interrupt request flag 8
Of the storage device masters 6 and 11 in the interrupt request flags 8 and 13 by changing the write data to the address assigned so that the storage device masters 6 and 11 in 13 and 13 can be accessed as one storage device. It is recommended that either one can be set to "1" or that both storage device masters 6 and 11 can be set to "1" at the same time.

[0056]

As described above, according to the present invention, it is possible to perform the function test of the interrupt control device without generating the interrupt request in the peripheral device, and thus, in the function test of the interrupt control device. Has the effect of simplifying the procedure for functional testing without the need to operate peripheral devices.

Further, since the peripheral device is not used, it is not necessary to wait for the period until the interrupt request is generated in the peripheral device, so that the time required for the functional test can be shortened.

Further, in the product development, even when the microcomputer in which only the peripheral is changed is formed without changing the interrupt controller itself, the function test of the interrupt controller does not depend on the peripheral device, and therefore the existing micro-computer is not used. There is an effect that the program for the computer function test can be used as it is, and the number of man-hours for creating the program in the function test can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a timing chart showing an operation of a conventional example.

FIG. 7 is a timing chart showing an operation of a conventional example.

FIG. 8 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 1 Central Processing Unit 2 Address Decoder 3 Arbitration Device 4, 9 Read / Write Control Device 5, 10 OR Gate 6, 11 Storage Device Master 7, 13 Storage Device Slave 8, 13 Interrupt Request Flag 14 Interrupt Control Device 15, 16 Peripheral Device

Claims (1)

[Claims] 1. A microcomputer comprising a central processing unit and an interrupt control unit corresponding to a plurality of peripheral devices, wherein an interrupt request from the peripheral devices is received and held, and a predetermined internal bus is provided. A first storage device that is writable from the central processing unit via an interface, and receives and holds an output of the first storage device;
A second storage device capable of writing / reading from the central processing unit via the internal bus; and a read / write control device performing a write / read control operation for the first and second storage devices. , At least in the interrupt control device,
It is possible to perform a function test of the interrupt control device via a specific interrupt control signal externally input to the read / write control device, without depending on an interrupt request from the peripheral device. Computer.