JP2593935B2 - Direct memory access device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a direct memory access device for performing direct memory access (DMA) transfer between an upper memory and a local memory.

(Prior Art) Direct memory access transfer is widely adopted as a data transfer means of an information processing apparatus.

<Conventional Multiprocessor System> FIG. 2 shows a block diagram of a conventional general multiprocessor system.

In this system, an upper processor 3 and an upper memory 4 are connected to an upper bus 1 via an upper bus interface unit 2. A plurality of lower processors 5 are connected to the upper processor 3 via the upper bus 1.

The lower processor 5 is connected to the upper bus 1 via an upper bus interface 2 ′ and an internal bus 7, to which a local memory 6 is connected. The lower processor 5 is composed of, for example, a microprocessor 80186 manufactured by Intel Corporation having a built-in DMA controller (DMAC).

In such a system, when performing the DMA transfer between the upper memory 4 and the local memory 6, roughly two means are taken.

The first means is that the lower processor 5
Start DMAC8. Then, after starting the DMA transfer, a right to use the upper bus 1 is requested to an upper bus arbitration unit (not shown). When the right to use the upper bus is acquired, predetermined information such as addresses and data is output on the upper bus 1. When a signal indicating the end of the data transfer is received from the upper memory 4, the right to use the upper bus 1 is relinquished at that point, and the operation of the DMAC 8 is terminated.

The second means first requests the right to use the upper bus 1 to an upper bus arbitration unit (not shown). Then, after acquiring the right to use the upper bus 1, the DMAC 8 built in the lower processor 5 is activated. Thereafter, DMA transfer is started, and predetermined information including an address and data is output onto the upper bus 1. When a signal indicating the end of the data transfer is received from the upper memory 4, the operation of the DMAC 8 is terminated at that time.

<First Conventional Means> FIG. 3 is a block diagram of a conventional DMA transfer means for executing the first means.

In this circuit, a local memory 6 is connected to a lower processor 5 via an internal bus 7, and when performing a DMA transfer with the upper memory 4, a request for a right to use the upper bus arbitration unit 9 is made. And blocks for performing necessary signal processing.

In the circuit shown in the figure, an interval timer 11, a DMA request generation circuit 12, a memory address decoder 13, a bus request generation circuit 14, an address buffer 15, a data buffer 16, and a memory ready signal buffer 17 are displayed.

The lower processor 5 uses the microprocessor 80186 with a built-in DMAC described above. The lower processor 5 uses the internal bus 7 to handle a total of 20-bit address signals and 16-bit data. In the figure, address upper bits A 'indicated as A19 to A16 are shown.
Output the upper 4 bits of the address signal.
An address signal A or data D is output to the lower 16-bit internal bus indicated as 15-0.

In the circuit shown in the figure, an interval timer 11 is a timer circuit for controlling the operation interval of the DMAC 8, and when a DMA transfer is requested, the DMA transfer is performed by the interval timer 11.
It is executed at the time interval set in. This is because the DMAC 8 continuously occupies the internal bus 7 for a long time and the lower processor 5
This is to prevent other operations from being hindered.

The DMA request generation circuit 12 is composed of a flip-flop and the like, and has a timer output TMO output from the interval timer 11.
And outputs a DMA request signal DRQ to the DMAC 8 of the lower processor 5. The memory address decoder 13 is composed of a theoretical circuit or the like which receives the address upper bit A 'output from the lower processor 5 and turns on the output when the address accesses the upper memory.

That is, in this system, the memory space is mapped so as to determine whether to access the local memory 6 or the upper memory 4 based on the upper bits of the address.

 FIG. 4 is an explanatory diagram of an example of the memory mapping.

As shown in the figure, the local memory real space is “00” in hexadecimal notation.
It occupies from “000” to “A0000”, a dummy space for upper memory write is provided up to “C0000”, a dummy space for upper memory read is provided up to “E0000”, and a space for system etc. is finally set to “FFFFF”. Thus, it is possible to determine whether to access the local memory 6 or the upper memory 4 from the upper 4 bits A 'of the address output from the lower processor 5 in FIG.

The output of the memory address decoder 13 is connected to the reset terminal of the DMA request generation circuit 12 and the bus request generation circuit.
Wired to input to 14 set terminals.

The bus request generation circuit 14 includes a flip-flop. Then, the output becomes a bus request signal BRQ. The reset terminal has a bus grant signal BG
Connected to input T.

On the other hand, address signals A and data D are output to the lower 16 bits of the internal bus 7, which are connected to be input to the address buffer 15 and the data buffer 16. Then, the address signal A and the data D are output to the upper memory 4.

Note that the bus select signal BGT is connected to the chip select terminals of the address buffer 15 and the data buffer 16 so as to be input.

<Operation of First Means> The above circuit operates according to the time chart shown in FIG.

First, the timer output from the interval timer 11 shown in FIG.
When TMO is output [Fig. 5 (a)], the DMA request generation circuit
12 is set, and the DMA request signal DRQ rises [FIG. 5 (b)]. This is DMAC8 built in lower processor 5.
, A read cycle of DMA transfer is started [FIG. 5 (c)].

The DMAC 8 occupies the internal bus 7, reads data from the local memory 6, and stores the data in a register (not shown) provided inside the lower processor 5. After the execution of the read cycle, the operation shifts to the write cycle [FIG. 5 (c)]. When the lower processor 5 outputs the address upper bit A 'assigned for accessing the upper memory 4 and the local memory 6, the lower processor 5 decodes the address to indicate that the access to the upper memory 4 has been performed.
13 recognizes and turns on the output to the bus request generation circuit 14. As a result, the bus request generation circuit 14 is set, and the bus request signal BRQ is output to the upper bus arbitration unit 9 (FIG. 5 (d)).

Since the output of the memory address decoder 13 is also output to the DMA request generation circuit 12, the DMA request generation circuit 1
2 is reset, and the DMA request signal falls [FIG. 5 (b)].

On the other hand, when the bus grant signal BGT is input from the upper bus arbitration unit 9 (FIG. 5 (e)), the bus request generation circuit
The bus request signal BRQ output from 14 is reset [FIG. 5 (d)]. The address buffer 15 and the data buffer 16 are operated by the bus grant signal, and the address signal A and the data D output from the lower processor 5 are output.
Is output to the upper memory 4 via the upper bus [FIGS. 5 (f) and 5 (g)]. When the write cycle is completed, the ready signal RDY is input from the upper memory 4 and input to the lower processor 5 via the memory ready signal buffer 17 (FIG. 5 (h)). Thereafter, the lower processor 5 relinquishes the right to use the upper bus and ends the DMA cycle.

<Second Conventional Means> FIG. 6 is a block diagram of a conventional DMA transfer means for executing the second means described above.

This circuit uses the timer output TMO of interval timer 11.
Is input to the bus request generation circuit 14, and this is output to the upper bus arbitration unit 9 as a bus request signal BRQ. The bus grant signal BGT input from the upper bus is input to the bus grant signal circuit 18,
This is configured to be input to the DMAC 8 of the lower processor 5. The DMAC 8 outputs a write request signal WR and a read request signal RD, which are connected together with the upper bit A 'of the internal bus 7 to the memory address decoder 13. Memory address decoder
The output of 13 is an address buffer 15 and a data buffer 16
Are connected so as to be input to the chip select terminal of.

<Operation of Second Means> FIG. 7 shows an operation time chart of the circuit of FIG.

In the circuit of FIG.
Is input to the bus request generation circuit 14 (FIG. 7A), the bus request signal BRQ is output from the bus request generation circuit 14 to the upper bus arbitration unit 9 [FIG. Fig. (B)]. When the right to use the upper bus can be acquired, the upper bus arbitration unit 9 outputs the bus grant signal.
BGT is output to the bus grant signal circuit 18 [No. 7
Figure (c)]. The output of the bus grant signal circuit 18 is input to the DMAC 8 of the lower processor 5 as a DMA request signal DRQ [FIG. 7 (d)]. Thereafter, the DMAC 8 starts a read cycle [FIG. 7 (e)], reads data from the local memory 6, and stores the data in a register inside the lower processor 5.

At this point, since the right to use the upper bus has already been acquired, the lower processor 5 outputs the address signal A to the address buffer 15 while giving the memory address decoder 13 an upper address for accessing the upper memory 4. The bit A 'and the write request signal WR are output. As a result, the memory address decoder 13
The address signal A and the data D are output to the upper memory 4 via the data buffer 15 and the data buffer 16. Thus,
A write cycle is executed [FIG. 7 (f),
(G)].

When the write cycle is completed, the ready signal RDY from the upper memory 4 is input to the lower processor 5 via the bus ready signal buffer 17 [FIG. 7 (h)]. Thus, the lower processor 5 relinquishes the right to use the upper bus and terminates the DMA cycle.

(Problems to be Solved by the Invention) The conventional means described above has the following problems.

First, in the first means shown in FIG. 3, after the DMAC 8 starts the DMA cycle, it acquires the right to use the upper bus, and the DMA cycle by the DMAC 8 does not end until a series of data transfer operations is completed.

That is, as shown in FIG. 5C, the internal bus 7 is used until the read cycle and the write cycle by the DMAC 8 are completed.
Is occupied and disturbs the lower processor 5. Therefore, for example, when a plurality of processors are connected to the upper bus and it takes a long time to acquire the right to use the upper bus, for example, several tens of μsec, the time for disturbing the lower processor 5 becomes longer. That is, during this time, the lower processor 5 cannot execute other processing. Therefore, there is a problem that the lower processor 5 cannot execute a process having a real time property, for example, a received character process accommodating a high-speed line.

On the other hand, in the second means shown in FIG. 6, after acquiring the right to use the upper bus, the DM built in the lower processor 5
This is a system that outputs a DMA request signal to AC8.
Therefore, for example, when the lower processor 5 is executing an instruction having a long execution time (POPA instruction or the like), or when accepting a hold request, the internal bus 7 is already occupied and the DMA request is Time will be suspended. Therefore, the upper bus continues to be occupied unnecessarily.

That is, as shown in FIG. 7, after the bus grant signal is input, the upper bus is disturbed until the read cycle and the write cycle are completed. If this takes a long time, the average data transfer capability of the upper bus itself decreases. There was a problem of letting them do.

The present invention has been made in view of the above points, and has as its object to provide a direct memory access device capable of setting the disturbance time of a lower processor and the disturbance time of an upper bus to a minimum.

(Means for Solving the Problems) A direct memory access device according to the present invention is provided with a DMA controller for receiving a DMA request signal, occupying an internal bus and accessing a local memory, and a DMA controller for accessing a higher-level memory and a local memory. A memory address decoder that inputs the upper bits of the address signal assigned to the DMA controller from the DMA controller, decodes the output, and outputs an upper access signal, and outputs a bus grant signal that inputs a bus request signal and permits the right to use the upper bus. A direct memory access device that includes a high-order bus arbitration unit and performs a DMA transfer between the high-order memory and the local memory; Reset by memory ready signal notifying release of memory A request generating circuit, a DMA request generating circuit which is set by a reset bus request generating circuit output and a timer output which is output at a set time interval, outputs a DMA request signal, and is reset by an upper access signal; When writing data to the upper memory, the data read from the local memory is latched by the upper access signal and output to the upper memory by the bus grant signal. When reading data from the upper memory, the data read from the upper memory is read. A data latch circuit that latches by a memory ready signal and outputs to a local memory by an upper access signal, and an address that latches an address signal of an upper memory to be accessed based on a bus request signal and outputs to an upper memory based on a bus grant signal Latch circuit , Enter the higher-level access signal,
And a ready signal generating unit for generating a ready signal for releasing the internal bus and outputting the ready signal to the DMA controller.

(Operation) In the above apparatus, first, when performing a write operation to the upper memory, the DMA controller accepts the DMA request signal and starts up. When the local memory starts reading, the read ends and the ready signal is input. Until the internal bus is occupied. On the other hand, the upper bus is occupied until a data write to a predetermined address is completed after a bus grant signal is output in response to a bus request signal. on the other hand,
The same applies to the read operation from the upper memory. As a result, the operation of writing to or reading from the upper memory and the operation of accessing the internal bus can be made independent of each other. As a result, the time for disturbing the lower processor and the time for disturbing the upper bus are both greatly reduced.

Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

<Configuration of Writing to Upper Memory> FIG. 1 is a functional block diagram of the direct memory access device of the present invention during a writing operation to the upper memory.

This circuit shows only circuit blocks that operate when data is written from the local memory 6 to the upper memory 4.

That is, a local memory 6 is connected to the lower processor 5 via an internal bus 7 in addition to an interval timer 11, a DMA request generation circuit 12, a memory address decoder 13, a bus request generation circuit 14,
An address latch circuit 35, a data latch circuit 36, a write address / data transmission timing generator 21 and a ready signal generator 22 are provided.

In addition, a DMA request mask circuit 23 composed of an AND gate is provided at a set terminal of the DMA request generation circuit 12, and an address latch mask circuit 24 composed of an AND circuit is provided at a set terminal of the address latch circuit 35. Have been.

In the above circuit, the output of the interval timer 11 and the output of the bus request
The input is connected to the set terminal of the DMA request generation circuit 12 via 3. The output of the DMA request generation circuit 12 is formed so as to be input to the DMAC 8 of the lower processor 5.

Further, the upper bits of the internal bus 7 are
Together with the write request signal WR output from the
And a memory address decoder as an upper address bit A 'assigned for access to the local memory 6.
Wired to input to 13. The output of the memory address decoder 13 is connected to be input to the reset terminal of the DMA request generation circuit 12, the set terminal of the bus request generation circuit 14, the ready signal generation unit 22, and the set terminal of the data latch circuit 36. .

The output of the bus request generation circuit 14 is output to the upper bus arbitration unit 9 as a bus request signal BRQ, and is also output to the address latch mask circuit 24. The address latch mask circuit 24 receives the address latch signal ALE output from the lower processor 5 together with the output of the bus request generation circuit 14, and is connected so that the logical product of the two is input to the set terminal of the address latch circuit 35. ing.

Further, the address latch circuit 35 and the data latch circuit 36
Are connected such that an address signal A and data D are respectively input via the lower 16 bits of the internal bus 7.

Furthermore, a buzz grant signal output by the upper bus arbitration unit 9
BGT is the write address / data transmission timing generator 2
The output of the write address / data transmission timing generator 21 is connected to the read enable terminals of the address latch circuit 35 and the data latch circuit 36.

The output of the ready signal generator 22 is connected to the DMAC 8 as a ready signal RDY, and the memory ready signal MRDY input from the upper memory 4 is connected to the reset terminal of the bus request generating circuit 14.

In the above circuit, the lower processor 5 and the local memory 6 have the same configuration as that used in the conventional apparatus described above with reference to FIG.
Have the same configuration.

DMA request generation circuit 12 and bus request generation circuit 14
Are circuits each composed of a flip-flop, which holds a signal input to a set terminal and whose output is reset by a signal input to a reset terminal. The memory address decoder 13 includes a logic circuit and the like,
When the address upper bit A 'and the write request signal WR are input, it is determined whether the access is to the upper memory 4 or the local memory 6, and in the case of access to the upper memory 4, an upper access signal SS is output. This allows DMA
Resets the request generation circuit 12 and sets the bus request generation circuit
14 and the data latch circuit 36, and the ready signal RDY
It is configured to output to C8. Note that the ready signal generation unit 22 includes a buffer amplifier and the like.

Each of the address latch circuit 35 and the data latch circuit 36 includes a register for temporarily latching the address signal A and the data D, and the like. These circuits latch data and the like when a data or the like is input and a higher access signal SS for data set is input, and a read enable signal
This circuit outputs the data according to the input of EN. The write address / data transmission timing generation unit 21
Receives the bus grant signal BGT and outputs the address signal A and the data D to the upper memory 4 at a timing in accordance with the interface specification of the upper bus, and after holding the bus grant signal BGT for a predetermined time, the address latch circuit 35 and the data latch circuit 36 And a shift register for outputting a read enable signal EN.

<Writing Operation to Upper Memory> The above circuit operates as follows.

FIG. 8 is a sequence chart illustrating a read operation of the device of the present invention.

(Step) First, the software of the lower processor 5 sets the operating conditions of the DMAC 8 incorporated therein. That is, a data transfer operation from the local memory 6 to the upper memory 4,
The conditions such as the read start address and the number of transfer words are set.

(Step) Then, the interval timer 11 is started. Interval timer 11 times out and timer output TMO
Is input to the set terminal of the DMA request generation circuit 12 via the DMA request mask circuit 23, the DMA request generation circuit 12 outputs a DMA request signal DRQ to the DMAC 8.

(Step) Upon receiving the DMA request signal DRQ, the DMAC 8 reads data to be written from the local memory 6 to the upper memory 4 in accordance with the settings made in the previous step (Step). This data is stored in a register (not shown) built in the lower processor 5.

(Step) Then, the address signal A for accessing the upper memory 4 is output to the address latch circuit 35, and the data D is output to the data latch circuit 36.

Further, the lower processor 5 sets the address upper bit A '
And a write request signal WR to the memory address decoder 13. The address upper bit A 'indicates access to the upper memory 4, an upper access signal SS is output from the memory address decoder 13, the DMA request generating circuit 12 is reset, and the bus request generating circuit 14
Is set, and the data input to the data latch circuit 36 is latched. On the other hand, the gate of the address latch mask circuit 24 is opened by the output of the bus request generation circuit 14, the address latch signal ALE output from the lower processor 5 is input to the set terminal of the address latch circuit 35, and the address signal A is latched. Is done. Further, the output of the memory address decoder 13 becomes a ready signal RDY through the ready signal generation unit 22 and is input to the DMAC 8.

As a result, the DMA request signal DRQ is turned off. Then, when the ready signal DRY is input to the DMAC 8 from the ready signal generation unit 22, the DMA cycle ends. Thereafter, the internal bus 7 occupied by the DMAC 8 is released.

(Step) Also, as a result of the bus request generation circuit 14 being set, its output closes the gate of the DMA request mask circuit 23,
Thereafter, the generation of DMA requests is prevented until the writing to the upper memory is completed.

On the other hand, the bus request signal BRQ output from the bus request generation circuit 14 is output to the upper bus arbitration unit 9.

(Step) When the right to use the upper bus is acquired, the upper bus arbitration unit 9
, The bus grant signal BGT is input to the write address / data transmission timing generator 21.

(Step) The write address / data transmission timing generation unit 21
Outputs the read enable signal EN at a predetermined timing,
The address signal A and the data D latched earlier are output from the address latch circuit 35 and the data latch circuit 36 to the upper memory 4.

(Step) In this way, the write operation to the upper memory 4 is executed,
When the write operation is completed, a memory ready signal MRDY for notifying the completion is input from the upper memory 4 to the bus request generation circuit 14. The bus request generation circuit 14 is reset by the memory ready signal MRDY, and opens the gate of the DMA request mask circuit 23.

At the same time, the output of the bus request signal BRQ is turned off, and the gate of the address latch mask circuit 24 is closed. Thus, the DMA from the local memory 6 to the upper memory 4
The transfer cycle ends.

During the above operation, the DMAC 8 starts up and the local memory 6
, The internal bus 7 is occupied until the ready signal RDY is input from the ready signal generator 22 to the DMAC 8. On the other hand, in the upper bus, after the bus grant signal BGT is input to the write address / data transmission timing generation unit 21, the memory ready signal MRDY is output to the bus request generation circuit.
It is occupied until 14 is entered.

That is, the access operation of the internal bus 7 and the access operation of the external bus are executed independently of each other. Comparing this with the operation timing of the conventional device shown in FIG. 5 or 7, it can be seen that both the time for disturbing the lower processor and the time for disturbing the upper bus are greatly reduced.

<Configuration of Reading from Upper Memory> FIG. 9 is a functional block diagram of a read operation from the upper memory of the device of the present invention.

This circuit shows only circuit blocks necessary for the operation of reading predetermined data from the upper memory 4 and transferring it to the local memory 6.

In the figure, a lower processor 5, a local memory 6, an internal bus 7, an interval timer 11, a DMA request generation circuit 12, a memory address decoder 13, a bus request generation circuit 14,
The address latch circuit 35, the data latch circuit 36, the ready signal generator 22, and the DMA request mask circuit 23 have the same configuration as the circuit shown in FIG.

Further, an I / O address decoder 25, a DMA request mask control circuit 26, a read address transmission timing generator 27, a DMA counter 28, and the like are added to this circuit.

In this circuit, memory address decoder 13 receives address upper bit A 'and read request signal RD input from lower processor 5, and outputs an upper access signal JS when reading data from upper memory 4. Have been. Further, the I / O address decoder 25 receives the address signal A and the write request signal WR input from the lower processor 5, and outputs a lower access signal KS or a count set signal CSL when writing data to the local memory 6. It is configured as follows. Both the memory address decoder 13 and the I / O address decoder 25 are constituted by predetermined logic circuits. Also, the DMA request mask control circuit 26
Is a circuit for controlling the opening / closing of the DMA request mask circuit 23, which is constituted by a flip-flop. The set terminal receives the upper access signal JS output from the memory address decoder 13 and the reset terminal receives the memory ready signal MRDY. Wired.

The bus request generating circuit 14 outputs a bus request signal BRQ to the upper bus arbitration unit 9 and, similarly to the example of FIG. 1, sends the bus request signal BRQ to the set terminal of the address latch circuit 35 via the address latch mask circuit 24. The output is connected.

In the case of this embodiment, the address latch mask circuit 24
Is composed of two AND gates 24a and 24b. The first AND gate 24a receives the inverted output of the bus request generation circuit 14 and the address latch signal ALE output from the lower processor 5, and calculates the logical product of them. Output to one AND gate 24b. AND gate 24b, AND gate
A logical AND of the output of the I / O address decoder 25 and the output of the I / O address decoder 25 is connected and output to the set terminal of the address latch circuit 35.

Also, the set terminal of the bus request generation circuit 14
A bus request mask circuit 31 including an OR gate 31a and an AND gate 31b is provided.

The OR gate 31a has the upper access signal JS output from the memory address decoder 13 and the I / O address decoder 25
And the lower access signal KS output from the AND gate 31b. An inverted output of the DMA counter 28 is connected to the AND gate 31b, and the output of the OR gate 31a is controlled to be opened and closed by the output signal of the DMA counter 28, and is input to the set terminal of the bus request generation circuit 14. It is connected as follows.

When the number of words to be transferred for DMA transfer is input from the lower processor 5, the DMA counter 28 receives the I / O address decoder 2
Set by the output of 5 and the memory address decoder 13
Is decremented by the output of the counter circuit.

Further, in this embodiment, the output of the memory address decoder 13 is connected so as to be inputted to the read enable terminal of the data latch circuit 36, and the set terminal of the data latch circuit 36 is connected so that the memory ready signal RDY is inputted. ing.

On the other hand, the baggage signal BGT input from the upper bus arbitration unit 9 is connected so as to be input to the read address transmission timing generation unit 27, and the output of the read address transmission timing generation unit 27 is used as a read enable signal of the address latch circuit 35. Wired to input to terminal.

The read address transmission timing generation unit 27
As in the case of the write address / data transmission timing generation unit 21 described in the figure, the bus grant signal BGT is delayed by a predetermined time in accordance with the operation timing of the upper bus, and is operated so as to be input to the read enable terminal of the address latch circuit 35. A circuit, for example, a shift register.

<Read Operation from Upper Memory> The above circuit operates as follows.

FIG. 10 is a sequence chart illustrating a read operation of the device of the present invention. Here, an example will be described in which data is DMA-transferred from the upper memory 4 to the local memory 6 in word units.

(Step) First, the following settings are made to the DMAC 8 incorporated therein by software of the lower processor 5.

That is, the storage start address of the local memory 6 is set in a destination pointer register (not shown). Next, "2" is added to the read start address of the upper memory, and the value is set in the source pointer register. Also, the number of transfer words is set in the transfer count register. Then, the fact that the mode is the memory-memory transfer mode and the fact that the mode is the word transfer mode are set in the control register.

(Step) Next, in a step, the count set signal CSL is output from the I / O address decoder 25 by software of the lower processor 5, and the number of transfer words WN is set to the DMA counter 28 using an I / O instruction. . in this case,
The set count value is a value obtained by subtracting “1” from the number of transfer words.

(Step) Next, the software of the lower processor 5 uses the I / O instruction to output the lower access signal KS from the I / O address decoder 25 to the read start address of the upper memory 4 to the address latch circuit 35. set. Further, an upper address bit A 'is input to the memory address decoder 13, and a read request signal RD output from the lower processor 5 is input. As a result, the memory address decoder 13 outputs the upper access signal JS, and the bus request generation circuit 14 is set via the OR gate 31a and the AND gate 31b.

(Step) As a result, the bus request generation circuit 14 outputs a bus request signal BRQ to the upper bus arbitration unit 9.

On the other hand, the DMA request mask control circuit 26 is set by the higher access signal JS output from the memory address decoder 13, the gate of the DMA request mask circuit 23 is closed, and the timer output TMO from the interval timer 11 is blocked. As a result, the DMA request signal DRQ is masked after this point.

(Step) Bus grant signal B responding to bus request signal BRQ
When the GT returns from the upper bus arbitration unit 9, the read address transmission timing generation unit 27 receives this and outputs a read enable signal to the address latch circuit 35 at a predetermined timing. Thus, first, the address latch circuit 35
Is output to the upper memory 4.

(Step) After that, when the data D is returned from the upper memory 4,
The data latch circuit 36 latches the data D by the memory ready signal MRDY input at the same time. Further, the memory ready signal MRDY is input to the reset terminal of the bus request generation circuit 14 to turn off the bus request signal BRQ.
Further, the memory ready signal MRDY is also input to the reset terminal of the DMA request mask control circuit 26. As a result, the gate of the DMA request mask circuit 23 opens, and subsequent DMA requests are permitted.

(Step) When the interval timer 11 times out after the DMA request is permitted, the timer output TMO becomes the DMA request mask circuit.
The signal is input to the set terminal of the DMA request generation circuit 12 via 23.

(Step) Next, the DMA request signal output from the DMA request generation circuit 12
When the DRQ is received by the DMAC 8, the DMAC 8 outputs the upper memory read start address + 2 set in the step previously on the internal bus 7.

By the way, in the step, the address latch circuit 35
Stores the read start address of the upper memory 4, whereby the data D is read and stored in the data latch circuit 36, and the data of the start address is pre-read before the DMA cycle of the DMAC 8 starts. .

When data is read in word units, the address is updated every two bytes, so the next read address for the upper memory 4 is a value obtained by adding "2" to the head address.
Therefore, as described above, the address of the start address + 2 is output to the address latch circuit 35 and latched.

When this upper address bit A 'is input to the memory address decoder 13 and the read request signal RD is input simultaneously,
The output of the memory address decoder 13 is input to the DMA request generation circuit 12, and the DMA request generation circuit 12 is reset.
As a result, the DMA request signal DRQ is turned off. On the other hand, the output of the memory address decoder 13 is input to a decrement terminal of the DMA counter 28, and the transfer word number of the DMA counter 28 is decremented.

(Step) Next, the read operation of the DMA cycle is terminated by the ready signal RDY input from the ready signal generation unit 22 to the DMAC 8 according to the output of the memory address decoder 13. Also,
The data read from the data latch circuit 36 is stored in the local memory 6 via the lower processor 5 by a DMA write cycle.

(Step) On the other hand, a bus request signal BRQ is output from the bus request generation circuit 14 set by the output of the memory address decoder 13 to the upper bus arbitration unit 9.
The bus request signal BRQ is transmitted to the address latch circuit 35
Is input to the address latch mask circuit 24 provided immediately before the set terminal, and the AND gate 24a is closed. Thereby, the address signal stored in the address latch circuit 35 thereafter is guaranteed.

(Step) After the bus request signal BRQ is output to the upper bus arbitration unit, the same operations as the steps described above are repeated from the above-described steps.

The operation from step to step is performed by the DMA counter 28
Repeatedly for the number of transfer words set in. DMA
When the count value of the counter 28 becomes “0”, the AND gate 31b of the bus request mask circuit 31 connected to the set terminal of the bus request generation circuit 14 closes. This masks the generation of the bus request signal BRQ for the next DMA transfer to be executed.

(Step) Since the count value of the DMA counter 28 is "1" smaller than the actual number of transfer words, the number of transfer current registers set in the DMAC 8 in the step does not reach even after the above step. Therefore, another DMA transfer cycle is executed. In this last DMA transfer, the same operation as the above steps is executed. However, in the step, the bus request signal
Since the BRQ mask condition is satisfied, the access operation to the upper memory unit is not actually performed.

That is, a state in which "1" is subtracted from the number of transfer words is stored in the DMA counter 28, and is decremented for each read. However, the DMA counter 28 is decremented for the first preceding read. No, finally DM
When the A counter becomes "0", the transfer of the required number of words is completed. Therefore, the subsequent output of the bus request signal BRQ is prevented, and malfunction is prevented.

That is, in the example of FIG. 10, the internal bus 7 to be used by the lower processor 5 is occupied until the ready signal RDY is input to the DMAC 8 after the DMA request signal DRQ is turned on. On the other hand, when the bus request signal BRQ is turned on and the bus grant signal BGT is input, the memory ready signal MRD
Occupied until Y is entered.

As a result of the above operation, similarly to the write operation to the upper memory explained in FIG. 1, in the read operation of FIG. 9, the access operation of the internal bus of the DMAC built in the lower processor 5 and the upper Access operations of the upper memory 4 via the memory can be made independent of each other.

Note that the actual device is one in which the functional blocks shown in FIG. 1 and the functional blocks shown in FIG. 9 are integrated.

In the above description, the description of the memory space of the upper memory is omitted, but it is possible to access a large-capacity upper memory by using a bank register or the like that specifies the upper memory address. Not even.

(Effects of the Invention) The direct memory access device of the present invention described above has an address latch circuit and a data latch circuit, so that the operation of the DMA controller built in the lower processor and the access operation to the upper memory can be performed. Can be independent. As a result, even when a plurality of processors are connected to the upper bus and each uses the upper bus to access the upper memory, the time during which each processor disturbs the operation when accessing the upper memory is reduced. You. In other words, the disturbing time of each processor is only the time corresponding to the local memory access, and is not affected by the state of the upper bus. Therefore, even when the lower processor executes a process requiring real-time performance, the influence of the state of the upper bus can be minimized. Further, the time when the lower processor uses the upper bus when accessing the upper memory is not affected by the state of the lower processor, and can be executed within the basic time of the memory transfer cycle of the upper bus. Therefore,
The influence on the deterioration of the upper bus data transfer capability can be minimized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a direct memory access device according to the present invention for writing to an upper memory, FIG. 2 is a block diagram of a conventional general multiprocessor system, FIG. 3 is a block diagram of a conventional DMA transfer means, 4 is an explanatory diagram showing an example of the memory mapping, FIG. 5 is an operation time chart of the circuit of FIG. 3, FIG. 6 is a block diagram showing another example of the conventional DMA transfer means, and FIG. 8 is a sequence chart showing a write operation of the device of the present invention, FIG. 9 is a functional block diagram of a read operation from the upper memory of the device of the present invention, and FIG. 10 is a functional block diagram of the present invention. 6 is a sequence chart of a read operation of the device. 4 upper memory, 5 lower processor, 6 local memory, 7 internal bus, 8 DMAC, 9 upper bus arbitration unit, 11 interval timer, 12 DMA request generation circuit , 13 ... Memory address decoder, 14 ... Bus request generation circuit, 21 ... Write address / data transmission timing generator, 22 ... Ready signal generator, 23
…… DMA request mask circuit, 24 …… Address latch mask circuit, 25 …… I / O address decoder, 26 …… DMA request mask control circuit, 27 …… Read address transmission timing generator, 28 …… DMA counter, 31 … Bus request mask circuit, 35… address latch circuit, 36… data latch circuit.

Claims (1)

(57) [Claims] A DMA controller for receiving a DMA request signal and occupying an internal bus to access a local memory;
Memory address decoder that inputs the upper bits of the address signal allocated for access to the upper memory and local memory from the DMA controller, decodes and outputs the higher access signal, and uses the upper bus by inputting the bus request signal A direct memory access device for performing a DMA transfer between a higher-level memory and a local memory, the higher-level bus arbitration unit outputting a bus grant signal for granting the right. Bus request generation circuit which is reset by a memory ready signal notifying the release of the upper bus output from the upper memory, and a timer which is output at a set time interval from the output of the reset bus request generation circuit DMA request signal set by the output A DMA request generation circuit that outputs and is reset by the upper access signal. When writing data to the upper memory, the data read from the local memory is latched by the upper access signal and output to the upper memory by the bus grant signal. When reading data from the upper memory, the data read circuit latches the data read from the upper memory by the memory ready signal and outputs the data to the local memory by the upper access signal. An address latch circuit that latches based on a bus request signal and outputs to the upper memory based on the bus grant signal, and receives the upper access signal, generates a ready signal for releasing the internal bus, and outputs the ready signal to the DMA controller Ready lady A direct memory access device comprising a signal generation unit.