KR100452325B1 - AMBA-based Multiprocessor system for processor identification number allocation and sequential booting - Google Patents

Abstract

The present invention assigns a unique number to each processor in a System On-Chip (SoC) using two or more processor cores using an Advanced Micro-controller Bus Architecture (AMBA) bus as a connection medium, and sequentially among a plurality of processors. A multiprocessor system capable of supporting in-boot is provided. This invention comprises a plurality of masters; A bus providing an address and control signal line to which the masters and other resources are connected, a read data signal line, and a write data signal line; A bus for receiving a bus request signal from the master to generate an internal bus request signal according to a bus activation signal, controlling whether a bus license is granted to each bus master, and outputting a bus user number of the master allowed to use the bus. Arbiter; And a multiprocessor supporting slave configured to provide a bus activation signal to the bus arbiter and to receive and store a bus user number from the bus arbiter.

Therefore, the present invention facilitates the implementation of a shared bus-based multiprocessor system using a plurality of ARM cores using the AMBA bus as a connection medium, and enables the operating system for a multiprocessor to be installed later.

Description

AMBA-based Multiprocessor system for processor identification number allocation and sequential booting}

The present invention relates to a multiprocessor system in a System On-Chip (SoC) using two or more processor cores using an Advanced Micro-controller Bus Architecture (AMBA) bus as a connection medium. The present invention relates to an AMBA bus-based multiprocessor system capable of assigning a unique number to each processor for implementation and supporting sequential booting among a plurality of processors.

In general, in order to construct a multiprocessor system using a plurality of processors, each processor must be assigned a unique number in the system. The unique number of each processor is essential for load balancing and interprocessor communication in a multiprocessor system. In addition, in a shared bus-based multiprocessor system, in which multiple processors share a system bus, a boot processor (BSP) may boot another processor after booting and initializing the system. Boot the system through sequential boot.

Intel's technical document, “Multiprocessor Specification,” describes processor unique number assignment and sequential booting as an example of an Intel processor (X86 architecture) in a shared bus-based multiprocessor system. Is as follows.

Intel processors have a device inside the processor called an Advanced Programmable Interrupt Controller (APIC) that shares an interrupt bus. The interrupt controller (APIC) finds its location information on the interrupt bus and stores it in an internal register, and the processor performs a read operation on the register so that the unique number on the interrupt bus can be known. The unique number obtained by each processor through the interrupt controller (APIC) is used later as the unique number of the processor after the operating system is loaded. With this, the multiprocessor operating system implements functions such as IPC and load balancing. .

An interrupt controller (APIC) enables sequential booting of processors in system boot in addition to processor unique number assignment. First, a processor using the largest value as a unique number is designated as a boot processor (BSP) to perform system boot and initialization, and the other processors are sequentially booted by the boot processor (BSP).

The AMBA bus and AMBA bus-based ARM processor cores, which are frequently used as internal buses of the System On-Chip, do not support the processor-specific number assignment function and the sequential boot function hardware described above. There is a problem that the implementation of the base multiprocessor system is not easy.

1 is a schematic diagram showing the configuration of a conventional AHB bus which is an AMBA bus.

The Advanced Micro-controller Bus Architecture (AMBA) bus, a system-on-chip bus structure developed and released by ARM, is an Advanced High-performance Bus (AHB) bus, an Advanced System Bus (ASB) bus, and an Advanced Peripheral Bus (APB) bus. Is done. The AHB bus is a backbone bus of a high performance system operating at a high speed clock, and the multiprocessor connection based thereon is a bus master that generates read and write requests over the bus, such as an ARM core processor or DMA device, as shown in FIG. The slaves 11-1 to 11-3 that perform the response to the read and write operations through the bus, such as the 10-1 to 10-3 and the memory controller, are the address and control signal mux 13 and the write data signal. The mux 14 and the read data signal mux 15 are connected to each other to communicate. At this time, each of the masters 10-1 through 10-3 makes a bus use request to the bus arbiter 12 to obtain a bus right, and if the request is accepted, performs a write or read operation through the bus.

The arbiter 12 receives a bus use request from the masters 10-1 to 10-3 to give a bus use permission to a specific master, and the path of the address and control signal mux 13 and the write data signal mux 14 Generate control signal for setting. After receiving the read or write request through the bus, the slaves 11-1 to 11-3 perform the corresponding operation, and in the case of the read operation, the slaves 11-1 to 11-3 read the read data through the read data mux 15. 10-3), the read data mux 15 selects one of the slaves 11-1 to 11-3 using the address signal from the output of the address and control signal mux 13; Controlled by

However, in the connection diagram as shown in FIG. 1, the masters 10-1 to 10-3, which are bus users, do not have resources to be assigned a unique number from the hardware constituting the bus. -3) cannot maintain unique number, and if each master is a processor, it can compete with each other at boot, so it is impossible to set permissions for system boot and initialization. Therefore, in the implementation of a multiprocessor system, the most basic processor unique number assignment and sequential booting are not possible.

The present invention has been proposed to solve the above problems, when configuring a multi-processor system based on the AMBA bus using a plurality of ARM processors to assign a processor unique number and to enable the sequential boot shared bus-based type It is an object of the present invention to provide an AMBA bus-based multiprocessor system that facilitates the implementation of a multiprocessor system and enables the operation of a multiprocessor system later.

In order to achieve the above object, the AMB bus-based multiprocessor system capable of assigning a processor number and sequentially booting the system comprises: a plurality of masters; A bus providing an address and control signal line to which the masters and other resources are connected, a read data signal line, and a write data signal line; A bus for receiving a bus request signal from the master to generate an internal bus request signal according to a bus activation signal, controlling whether a bus license is granted to each bus master, and outputting a bus user number of the master allowed to use the bus. Arbiter; And a multiprocessor supporting slave configured to provide a bus activation signal to the bus arbiter, and receive and store a bus user number from the bus arbiter.

The bus arbiter may be configured to perform an AND operation on a bus request signal input from the masters and a bus activation signal input from the multiprocessor support slave, and generate a plurality of end gates to generate an internal bus request signal. And arbitration logic to arbitrate bus usage, output a bus permission signal to the corresponding master, and provide a bus user number of the bus licensed master, wherein the multiprocessor capable slave is a bus interface for interfacing with the bus. part; An address translation and register controller for generating a control signal for controlling a register by decoding an address input through the bus interface; A bus enable register for providing the bus enable signal; A bus user number register for receiving and storing a bus user number from the bus arbiter; And a master for read data for providing the corresponding data through the bus interface unit according to the address translation and the control of the register controller when the master requests the register read.

1 is a conventional AHB-based bus connection diagram,

2 is an AHB based multiprocessor system configuration using an arbiter and multiprocessor functional support hardware according to the present invention;

3 is a block diagram illustrating an arbiter supporting sequential booting according to the present invention;

4 is a block diagram of a hardware supporting multiprocessor functions according to the present invention;

5 is a timing diagram showing a basic cycle of an AHB-based bus to which the present invention is applied;

6 is a timing diagram illustrating an arbitration cycle of an AHB based bus to which the present invention is applied.

Explanation of symbols on the main parts of the drawings

210-1 ~ 210-3; Processor 220-1,220-2; Slave

230; Arbitrator 240; Address and control mux

250; write data mux 260; read data mux

270; Decoder 280; Multiprocessor Slave

231--233; Endgate 235; Arbitration Logic

281; AHB bus slave interface 282; address resolution and register controller

283 Bus Bus Register 284 Bus Enable Register

285; mux for read data

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is an AHB-based multiprocessor system configuration using an arbiter and multiprocessor functional support hardware according to the present invention.

Referring to FIG. 2, the AHB-based multiprocessor system to which the present invention is applied may include bus masters 210-1 to 210-3, slaves 220-1 and 220-2, improved arbiter 230, addresses and control signals. The mux 240, the write data signal mux 250, the read data signal mux 260, the decoder 270, and the multiprocessor support slave 280.

Here, each of the masters 210-1 to 210-3 is CPU cores for implementing a multiprocessor, and the multiprocessor supporting slave 280 is equipped with a function for supporting multiprocessor booting according to the present invention. It can be seen that the improved slave is connected to each other by the improved arbiter 230, the bus user number Bus_ID, and the bus activation signal Bus_enable.

That is, the present invention provides an improved arbiter 230 that improves the arbiter function in order to support processor unique number allocation and sequential boot function in the conventional AHB infrastructure, and reads and reads the control register for limiting the arbitration function. The multiprocessor capable hardware 280 supporting the write function is used.

3 is a block diagram illustrating an arbiter supporting sequential booting according to the present invention.

The arbiter 230 according to the present invention is an improvement of the arbiter used in the existing ASYB (AMB Example AMBA System), and the bus use request signals Bus_Req0 to Bus_Reqn from the master modules 210-1 to 210-3. And the bus enable signals Bus_en0 to Bus_enn from the multiprocessor function support hardware 280. The bus request signal and bus enable signal generate an internally used bus request signal through the AND gate logic 231, 232, 233 inside the improved arbiter.

In this case, when the bus enable signals Bus_en0 to Bus_enn received from the multiprocessor capable hardware 280 are logic '0', the arbitration logic 235 is performed even if the corresponding bus request signals Bus_Req0 to Bus_Reqn are driven to logic '1'. The bus request signal, which is inputted into, is driven by logic '0' so that the bus request is ignored.

As such, the bus enable signals (Bus_en0 to Bus_enn) input from the multiprocessor capable hardware 280 are used to perform a function as a boot processor (BSP) by allowing only a specific bus user to use a bus license during initial boot and initialization of the system. After the booting of the boot processor (BSP) is completed, a write operation is performed to the bus enable register (224 of FIG. 4) of the multiprocessor capable hardware 280 to sequentially enable bus usage of other bus users to sequentially boot. To make it possible.

The enhanced arbiter 230 also performs the function of passing the user number (Bus_Master_ID) of the selected bus to the multiprocessor functional support hardware 280 at every arbitration point, and the multiprocessor functional support hardware 280 provides improved arbitration. The mediation result is received from the device 230 and stored in the bus user number register (223 of FIG. 4).

4 is a block diagram of a hardware supporting multiprocessor function according to the present invention. Referring to FIG. 4, the multiprocessor functional support hardware 280 includes an AHB bus slave interface 281, an address read and register controller 282, a mux 285 for read data, a bus enable register 284 and a bus user number. It consists of a register 283.

The AHB bus slave interface logic 281 uses address and control signals, write data signals (Wdata), and read data signals (Rdata) to receive and respond to read and write requests in accordance with the AHB bus protocol. It is the same logic as the slave interface of EASY. The select signal (Select) is a slave selection signal received from the AMBA bus decoder 270 according to the address map. When the address currently driven on the bus designates the multiprocessor function support hardware 280, Driven to 1 '.

The address read and register controller 282 generates the read and write control signals of the bus enable register 284 and the bus user number register 283 by using the received address information and the bus control signal. The mux 285 for read data is controlled.

The bus enable register 284 is a register that can be read and written by the masters 210-1 to 210-3, and each bit is used as an activation mask signal for each bus user. The contents of the bus activation register 284 are transmitted to the arbiter 230 improved by the bus activation signals Bus_en0 to Bus_enn of each bus master to indicate whether bus usage rights are activated.

After the reset, the bus enable register 284 is initialized with only the least significant bit set to logic '1' and all others are initialized to logic '0'. Therefore, the bus license is only available to bus user 0 of the bus enable signals Bus_en0 to Bus_enn. Will be given. Therefore, the processor connected to bus user 0 uses the bus exclusively, and after booting and system initialization, sequentially writes logic bits '1' to the other bits except the least significant bit of the bus enable register 284 through a write operation. This setting allows multiple processors to sequentially boot the bus by allowing the other processors to use the bus sequentially.

The bus user number register 283 performs a function of latching the bus user number Bus_Master_ID received from the improved bus arbiter 230 when the select signal Select received from the decoder 270 is logic '1'. do. When a specific bus master reads the bus number register 283 in a read operation, the decoder 270 drives the select signal Select to logic '1' with the multiprocessor capable hardware 280. The AHB slave interface logic 281 of the multiprocessor functional support hardware 280 will receive a read request.

As the select signal Select is driven to logic '1', the bus user number register 283 latches the bus user number Bus_Master_ID received from the improved arbiter 230 and reads the latched contents for read data. A response is made through the mux 285. Therefore, a specific master can naturally recognize its own bus user number by performing a read operation on the bus user number register 283, and can use it as a processor unique number.

5 is a timing diagram showing the basic cycle of the AHB-based bus to which the present invention is applied.

Referring to the drawings, one bus cycle is composed of an address period and a data phase, and an address ADDR [31: 0] and a control signal Control which are an operation target in the address period. It can be seen that the write data WDATA [31: 0] or the read data RDATA [31: 0] are activated in the data period after is activated. In this case, the device providing the data in the read operation informs that the data is ready through the ready signal.

6 is a timing diagram illustrating an arbitration cycle in an AHB based bus to which the present invention is applied.

Referring to the drawing, the masters 210-1 to 210-3 using the bus activate the bus use request signal BUSREQx requesting the arbiter 230 to use the bus. After arbitration according to the algorithm, the bus license signal (GRANTx) is activated to the master. Accordingly, the master acquires a bus license and performs a read or write operation.

As described above, according to the present invention, in order to implement an AMBA bus-based multiprocessor system in an SoC design using a plurality of ARM processors, each processor may be assigned a unique number and may support sequential booting. The present invention facilitates the implementation of a shared bus-based multiprocessor system using a plurality of ARM cores using an AMBA bus as a connection medium, and enables an operating system for a multiprocessor in the future.

What has been described above is only one embodiment describing an AMB bus-based multiprocessor system capable of assigning processor numbers and sequentially booting according to the present invention, and the present invention is not limited to the above embodiments, and the following patents are provided. Without departing from the gist of the present invention claimed in the claims, anyone of ordinary skill in the art to which the present invention extends to the spirit of the present invention to the extent that various modifications can be made.

Claims (5)

Multiple masters; A bus providing an address and control signal line to which the masters and other resources are connected, a read data signal line, and a write data signal line; A bus for receiving a bus request signal from the master to generate an internal bus request signal according to a bus activation signal, controlling whether a bus license is granted to each bus master, and outputting a bus user number of the master allowed to use the bus. Arbiter; And A multiprocessor capable slave providing a bus activation signal to the bus arbiter and receiving and storing a bus user number from the bus arbiter; AMB bus-based multiprocessor system capable of assigning processor numbers and sequential boot. The method of claim 1, wherein the bus arbiter, Arbitrarily multiplies the bus request signals input from the masters and the bus activation signals input from the multiprocessor capable slaves and arbitrates bus usage according to the outputs of the endgates; And an arbitration logic that outputs a bus permission signal to the corresponding master and provides a bus user number of the master who has obtained the bus license. The method of claim 1, wherein the multiprocessor support slave, A bus interface unit for interfacing with the bus; An address translation and register controller for generating a control signal for controlling a register by decoding an address input through the bus interface; A bus enable register for providing the bus enable signal; A bus user number register for receiving and storing a bus user number from the bus arbiter; And When masters require a register read, the read data mux for providing the corresponding data through the bus interface unit under the address translation and the control of the register controller; processor number assignment and sequentially bootable AMB A-bus based multiprocessor system. 4. The method of claim 3, wherein the contents of the bus activation raster are set to a reset initialization value of only a specific bit logic '1' and the rest of the logic '0' to provide exclusive permission for a bus master to which a specific processor is connected. After a licensed processor has booted and system initialized as a boot processor, it sequentially sets a specific bit in the bus enable register to logic '1' to allow other processors to use the bus sequentially. AMB bus-based multiprocessor system capable of sequentially assigning processor numbers and booting sequentially. The system of claim 3, wherein the multiprocessor system comprises: A specific processor acquires a bus user number through a read operation of the bus user number storage register, and assigns the bus user number as a processor unique number to use for interprocessor communication and other multiprocessor program development. AMB bus-based multiprocessor system with processor number assignment and sequential boot.