JPH02244342A - Trace for branch instruction - Google Patents

Abstract

PURPOSE:To improve the storage efficiency of a buffer for tracing by gathering only effective information without storing the repetition of unnecessary data in the buffer for tracing. CONSTITUTION:Every time the branch instruction is executed, a comparator 17 compares the contents of a save address register 3 which are data to be traced with the contents of a trace copy register 6. When the comparison result of the comparator 17 shows a coincidence, '000' is set in a trace address low- order register 51. Consequently, the storage address of the buffer 4 for tracing is returned and next trace data is overwritten on trace data which is stored in this range. When the comparison result of the comparator 17 does not show the coincidence, the value of the save address register 3 is stored in the buffer 4 for tracing. Consequently, data is prevented from being stored repeatedly and the buffer for tracing can be used effectively.

Description

[Detailed Description of the Invention] [Summary] Regarding a tracer that traces the branch destination of a branch instruction in an information processing device, the present invention aims to improve the buffer storage efficiency by not storing unnecessary data repetitions in the buffer. A save address register that copies and holds the value of the address register when a branch instruction is executed, a trace buffer that stores the data to be traced, a trace address register that holds the storage address of the trace buffer, and a save address register. a trace copy register that copies and holds the value of the trace address register, a comparator I that compares the value of the save address register with the value of the trace copy register, and the value of the lower one digit of the trace address register and the value immediately before a predetermined reference value. and a comparator (2) for comparing the value of the trace address register with the value of the reference value, and when the value of the lower one digit of the trace address register is the reference value, the data to be traced is copied and held in the trace copy register, and each time a branch instruction is executed. Next, compare the value of the save address register that holds the data to be traced with the value of the trace copy register, and if they are the same, return the trace address by setting the reference value in the lower 1 digit of the trace address register. , if the comparison results are not the same, the contents of the save address register are stored in the trace buffer.

[Industrial application field]

The present invention relates to a tracer that traces a branch destination of a branch instruction in an information processing device.

[Conventional technology]

In an information processing device, when a branch instruction is executed, the branch destination address of the branch instruction is stored and used for diagnosis, debugging, and the like.

In a processing device of a certain size or larger, this is generally performed by a service processor or the like.

In a C3 (control storage) or the like that stores a microprogram, when a branch instruction is executed, a method of storing the branch destination in a trace buffer and tracing it is a conventional technique.

[Problem to be solved by the invention]

In conventional tracers such as those mentioned above, when a program is in a loop, branch instructions are often used, so the trace buffer quickly fills up with repeated contents, making it difficult to use as a tracer. There is a problem that it becomes impossible to fully fulfill the function of

The problem to be solved by the present invention is to provide a branch instruction tracer that eliminates such conventional problems.

[Means to solve the problem] FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 1 is a program memory that stores programs.

2 is an address register that holds the address of the next instruction to be executed.

3 is a save address register, which copies and holds the value of the address register when a branch instruction is executed.

Reference numeral 4 is a trace buffer that stores branch destinations to be traced.

A trace address register 5 holds the storage address of the trace buffer and is incremented every time a branch instruction is executed.

Reference numeral 51 is a trace address lower register, which is a register for the lower n digits of the trace address register 5.

A trace copy register 6 copies and holds the contents of the save address register 3.

A comparator I 7 compares the value of the save address register 3 and the value of the trace copy register 6.

8 is a comparator ■, and trace address lower register 5
The value of 1 is compared with the previous value of a predetermined reference value.

[For production]

In the present invention, a certain range is set in the trace buffer 4 based on a reference value determined as the value of the lower one digit of the trace address register 5, and the presence or absence of a loop is detected by comparing it with the first data of the range. .

For example, the value of the lower three digits of the trace address register is
When “ooo” (the next timing when comparator ■8 compares the lower three digits of the trace address register with “111” and a match is obtained), the data to be traced (branch destination address) is copied to the trace copy register 6 and held.

Every time a branch instruction is executed, the contents of the save address register 3, which is the data to be traced, and the trace copy register 6
The contents of are compared by comparator I7.

As a result of the comparison by the comparator 7, if they match, "000" is set in the trace address lower register 51. As a result, the storage address of the trace buffer 4 is returned, and the trace data stored in this range is overwritten with the next trace data.

As a result of the comparison by the comparator I7, if there is no match, the value of the save address register 3 is stored in the trace buffer 4.

Next, the value of the trace address lower register 51 is updated.

With the above configuration, it is possible to prevent the storage of duplicate data and effectively use the trace buffer.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 to 5.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

In the figure, 1 is the control storage (C8) and 2 is the control storage address register (C8).
CSA). 3 is the save address register (SV
A).

A local storage (LS) 4 stores trace data.

51 is a trace address lower register (TRAL), 52 is a trace address upper register (TRAL)
It is.

A trace copy register (TRC) 6 copies the value of 5VA3 in response to a control signal CLG.

7 is a comparator I, which compares the value of 5VA3 and the value of TRC6. If they match, a match signal TRC is output.

8 is a comparator (2), which adds the value of TRAL51 and the output of adder 11.

9 is the trace address space register (,TRAB)
, and stores the reference value of the lower n digits of the trace address. This reference value is variable and is updated every address interval set in the trace address interval register TRA110.

Reference numeral 10 denotes a trace address interval register (TRAI), which sets a trace address range for detecting program loops.

11 is an adder, which combines the value of TRAB9 and TRA110
Add the values of .

In this example, T, RAB9. TRAll0 and adder I'll allow the trace address interval to be set arbitrarily without being constrained by the number determined by the number of digits of TRAUIO.

A trace address information register (TRI) 12 stores information such as the number of loops.

A branch success flip-flop 13 is set by a branch success signal (BS) and outputs a branch success copy signal.

The solid lines in the figure indicate data lines, and the broken lines indicate control lines.

○ in the data input of LS4 and the input of TRAL51
Marks indicate multiplex control signals. The data input of LS4 is normally from 5VA3, but when the match signal TRAC of comparator 8 is output, it is switched to the TR112 side that stores information such as the number of loops. TRAL5
The input of 1 is incremented by the +1 adder, but TRABQ is incremented by the match signal TRC from comparator I7.
can be switched to the side.

The AND signal of the coincidence output TRAC and BS of the comparator ■8,
The signal CLG is output by ANDing with the clock CLK, and T
A copy is taken to RC6 and TRAB9 is updated.

The operation of the embodiment shown in FIG. 2 will be explained below.

(1) First, TRAll0, TRAL51, TRAB
9. Reset the contents of TRll01TRC6 and C3A2.5VA3.

(2) Although it is possible to give a fixed value to TRA I 10 or rewrite it as necessary, it is set to "7'" in this operation example. The initial value of TRAB9 is "0".

(3) When a branch instruction is executed in control storage (C3) 1, the value of C3A2 is copied to 5VA3. Further, since the branch success signal BS is turned on, the flip-flop 13 is set, and the branch success copy signal BSC is turned on at the next timing.

(4) Comparator I7, TRC6 (7) contents and 5V
The contents of A3 are compared. If the compared contents are the same, copy the value of TRABII to TRAL51 and
Increment 0 by 1. If the compared contents are not the same, TRAL51 is incremented by one.

(5) At the next timing after step (4), the value of 5VA3 is written to the local storage (LS) 4.

(6) If the comparison result by comparator ■8 is a match, +1 is added to the output of adder 11 at the next timing, the value of TRAB9 is updated with that value at the next timing, and the contents of 5VA3 are updated. Copied to TRC6.

FIG. 3 is a diagram showing the flow of a program as an operation example of an embodiment of the present invention.

FIG. 4 is a time chart 2 showing the operation when the program flow shown in FIG. 3 is processed according to an embodiment of the present invention.

As shown in FIG. 3, branches are made in the order of ■■■■■■■■■■, and the timing of each signal (data) when the program is executed is as shown in FIG.

A branch success copy signal (BSC) is output one timing later than the branch success signal (BS).

The contents of the save address register (SVA) 3 become ■■■■■■■■■■ as the program is executed.

Since the content of TRAL51 is initially the TR112 side value "0°", the value ■ of 5VA3 is copied to the TRC6 (timing 3), and the trace data ■ is stored at address O of LS (timing 4).

Subsequently, at timing 6, trace data ■ is stored at address 1.

The value of 5VA3 and the value of TRC6 are compared for each successful branch, and at timing 7, a match is found between ■ and ■, and TR
The value of AL51 is set to 0''. At the same time, the value of TR112, which stores information on the number of loops, is incremented by 1.

Therefore, at timing 8, trace data ■ is overwritten at address 0 of LS4, and at timing 10, address 1 is overwritten.
■ is overwritten (the monitor at address 1 is changed from ■ to ■).

Thereafter, trace data (1) to (2) are similarly stored at addresses 2 to 6 of LS4.

In this example, the value of TRAll0 is set to “7”,
At timing 20, when the value of TRAL51 becomes "7", a match is found in comparator ■8 and a match signal TRAC is output, and at the next timing, the input of LS4 becomes TR112.
The contents of TR112 are stored.

At the same time, "8" is set in TRAB9, and this is set in TRAL51.

At timing 22, trace data ■ is written to address 8 of LS4.

FIG. 5 is a diagram showing trace results according to an embodiment of the present invention. This figure shows an example where the trace address interval is set to 7.

As shown in the figure, the tracer address (LS4 storage address) xxxxo contains the reference trace data (
In Figure 4, ■) 1 is recorded, and addresses XXX1 to XX
X6 has normal trace data ii (in Fig. 4
■■■) are recorded.

At address XXX7 of the tracer, a flag 1:i indicating the presence or absence of a loop and data iv are recorded in the first bit.

When the flag ■ is "0", it indicates that there is no loop through the trace data 11ji, and indicates that the data iv is trace data.

When the flag 111 is "1", it indicates that the trace data has been repeated, data iv indicates the number of repetitions, and trace data ii indicates the trace data that finally exited the repeating state.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, unnecessary data repetitions are not stored in the trace buffer, and only valid information is collected, thereby improving the storage efficiency of the trace buffer. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a diagram showing the configuration of one embodiment of the present invention, and FIG. 3 is a diagram showing the flow of a program as an example of operation of one embodiment of the present invention. , FIG. 4 is a time chart showing a processing example according to an embodiment of the present invention, and FIG. 5 is a diagram showing trace results according to an embodiment of the present invention. In the figure, 1 is the program memory (control storage C3
), 2 is the address register (C3A), 3 is the save address register (SVA), 4 is the trace buffer (local storage LS), 5 is the trace address register, 6 is the trace copy register (TRC), 7.8 is the comparison 11 is an adder, 9 is a trace address reference register (TRAB), 10 is a trace address interval register (TRAI), 12 is a trace address information register (TRI), 13 is a flip-flop, 51 is a trace address lower register (TRAL) ), 5
2 indicates a trace address upper register (TRAU). 1 is a diagram showing the configuration of the present invention; FIG. 1 is a diagram showing the flow of a program as an example of the operation of an embodiment of the present invention; figure

Claims (1)

[Claims] When a branch instruction is executed, the branch destination program memory (
1) A branch instruction tracer that stores the internal address in a trace buffer (4), and a save address register (3) that copies and holds the value of the address register (2) when a branch instruction is executed; Trace buffer (
4), a trace address register (5) that holds the storage address of the trace buffer and increments each time a branch instruction is executed, and a trace copy register (6) that copies and holds the value of the save address register (3). , a comparator I (7) that compares the value of the save address register (3) and the value of the trace copy register (6), and a comparator I (7) that compares the value of the lower n digits of the trace address register (5) with a predetermined reference value. a comparator II (8) that compares the previous value with the previous value, and copies the data to be traced to the trace copy register (6) when the value of the lower n digits of the trace address register (5) is the reference value. The value of the save address register (3) which holds the next data to be traced is compared with the value of the trace copy register (6) each time a branch instruction is executed, and if they are the same, the trace address register is (5
) by setting the reference value in the lower n digits of the trace address, and if the comparison results are not the same, the contents of the save address register (3) are saved in the trace buffer (
4) A branch instruction tracer characterized in that it is configured to be stored in a branch instruction tracer.