JPS62288946A - Jump log recording system - Google Patents

Abstract

PURPOSE:To facilitate reducing and understanding the quantity of recorded information by discriminating the same loop in accordance with conditional jump instructions and the number of unconditional jump instructions between two conditional jump instructions to record the number of times of repeated processing also. CONSTITUTION:A jump instruction detecting means 100 discriminates the jump instruction executed in the processing process and the jump condition to output jump information jd. A jump information control means 200 holds information jd, which the means 100 outputs when detecting the conditional jump instruction and collates it with next output information jd. A jump counting control means 300 counts and stores the number of unconditional jump instructions detected between two continuously detected conditional jump instructions and collates it with the next counted number of unconditional jump instructions. A memory control means 400 counts the number of time of repeat and stores it in a memory 1 when collation in the means 200 results in coincidence and that in the means 300 results in coincidence. Thus, jump information is not recorded repeatedly but the number of times of repeat is recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In an apparatus that records a processing process by a jump destination address of a jump instruction and a jump destination address, a conditional jump instruction and a jump destination address between two conditional jump instructions are provided. By identifying the same loop based on the number of unconditional jump instructions and recording the number of repetitions, it is possible to reduce the recording amount and facilitate understanding.

[Industrial application field]

The present invention relates to an improvement in a jump history recording method in an apparatus for recording processing steps using jump information.

2. Description of the Related Art In the development stage of a program to be executed by an information processing device or the like, the normality of the program is confirmed by executing the program by the processing device or the like and recording the processing process.

In such a process, when a jump instruction is executed, the process is determined by recording a jump destination address and jump information indicating the jump destination address.

When recording such jump information, it is desirable to record the minimum necessary information in a state where the processing process is easy to understand.

[Conventional technology]

In a conventional jump history recording method, jump information is sequentially recorded in a memory for all jump instructions detected in a target processing process.

For example, when recording a processing process as shown in FIG. 11" is added to i (step S3), and in step S4, the condition (i =
10000> is not satisfied, when a conditional jump instruction JX to jump from address E to address D is detected, the recording device stores the memory (MEM) as shown in FIG.
) Jump information jd (E-D) including jump destination address E and jump destination address D at address a=l of 1
Store.

After executing conditional jump instruction JX and process 2 (steps S4 and S5), unconditional jump instruction J jumps from address F to address A in step S6.
When C is detected, the recording device stores jump information jd(F-A) including jump destination address F and jump destination address A at address a-r2J of memory (MEM) 1, as shown in FIG. do.

Similarly, in the process of steps S6 to SIO, the recording device detects unconditional jump commands JB and JC in steps S8 and S10, and
Jump information jd (H-B) and jd (G=
C) is stored.

Similarly, in step S4, the condition (i=10
000> is satisfied, the processing from step S2 to SIO is repeatedly executed 9999 times, and the recording device stores the memory.
(MEM) Jump information jd (E-D) to j, d (GC) stored in addresses mini to 4 of 1 to the area from address a=r5J to "39996", 999
Store repeatedly 9 times.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional jump history recording method, jump information corresponding to all jump instructions detected in the processing process to be recorded is recorded.
jd is recorded in the detection order.

Therefore, the process is repeated many times (so-called loop).
is included, the jump information jd corresponding to the jump instruction detected during repeated processing will be recorded for the number of repetitions, and the required storage capacity of the recording memory will also increase, making it difficult to understand the processing process. It will be recorded in a difficult condition.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.゛In Fig. 1, 1 is a memory for recording jump information jd, and ■ is an instruction that is executed sequentially in the processing process to be recorded.

Reference numerals 100, 200, 300 and 400 are jump command detection means, jump information control means, jump count control means and memory control means provided according to the present invention, respectively.

Jump instruction detection means 100 identifies jump instructions and jump conditions to be executed in the process, and outputs jump information jd.

The jump information control means 200 holds the jump information @jd output when the jump instruction detection means 100 detects a conditional jump instruction, and collates it with the jump information jd of the conditional jump instruction to be output next time.

The jump count control means 300 counts and accumulates the number of unconditional jump instructions detected between two conditional jump instructions successively detected by the jump instruction detection means 100, and compares it with the number of unconditional jump instructions to be counted next time.

The memory control means 400 is the jump information control means 200
When the matching result of the jump counting control means 300 and the matching result of the jump counting control means 300 both show a match, it is determined that the same processing process has been repeatedly executed, and the number of repetitions is counted and stored in the memory l.

[Effect]

Therefore, even when the same processing process is repeatedly executed many times, the number of repetitions is recorded instead of repeatedly recording jump information, which greatly reduces the storage capacity required for recording memory. It becomes possible to record easily.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a recording apparatus according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the timing control process in FIG. 2, and FIG. 4 is a diagram showing a jump counting control process in FIG. 5 is a diagram showing an example of the jump information control process in FIG. 2, FIG. 6 is a diagram showing an example of the memory control process in FIG. 2, and FIG. 7 is a diagram showing an example of the memory control process in FIG. FIG. 2 is a diagram showing recording results according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a jump command detection section (JPC) 2 is provided as a jump command detection means 100, and a jump count control section (JCC) 4 is provided as a jump count control means 300.
A jump information control section (JDC) 5 is provided as jump information control means 200, and a memory control section (MMC) 6 is provided as memory control means 400.

The jump count control unit (JCC) 4 includes a register (JCRI) that stores the number n1 of unconditional jump instructions in the current loop.
41 and a register (JCR2) 42 for accumulating the number n2 of unconditional jump instructions in the previous loop.
A register (JDR) 51 is provided to store the jump information storage address a1, and a register (JDPR) 51 is provided in the memory control unit (MMC) 6 to store the jump information storage address a1, and a register (JDPR) 51 to store the jump information storage address a1 is stored.
LCPR) 62 is provided.

In the initial state, the number n1 of unconditional jump instructions in the current loop, the number 02 of unconditional jump instructions in the previous loop, and the number of loops n3 are all set to "0", and the jump information storage address al and the loop number storage address a2 are both set to "0". is set to "1", and no jump information jd is stored in the previous condition jump information register (JDR) 51.

2 to 6, the jump instruction detection unit (JP
C) 2 monitors each executed instruction I in the processing process to be recorded, and when a jump instruction is detected, transmits a jump instruction detection signal j to the timing control unit (TC) 3.
Set pl to logic “1” and output jump information jd including the jump source address and jump destination address,
Jump information control unit (JDC) 5 and memory control unit (
MMC) 6. Furthermore, a jump instruction detection unit (JP
C) 2, if the detected jump instruction is a conditional jump instruction, the jump instruction detection signal jp2 also becomes logic "1".
” and transmits it to the timing control unit (TC) 3 together with the jump command detection signal jpl.

It is assumed that each execution command in the process shown in FIG. 8 is transmitted to the jump command detection unit (JPC) 2.

When the conditional jump instruction JX is detected in step S4 of FIG. 8, the jump instruction detection signals jp1 and jp
2 are both set to logic "1", and jump information jd
(E-D) is output.

In the timing control unit (TC) 3, when both the jump command detection signals jpl and jp2 are set to logic "O", the timing signals t1 to t4 are all set to logic "0". However, the jump instruction detection signal jpl is set to logic "1" (step 531).
), and when the jump instruction detection signal jp2 is set to logic "1" (step 532), the timing signal t2 is set to logic "1" as shown in FIG. 3 (step 53).
3).

In the jump counting control section (JCC) 4, as shown in FIG. 4, the timing signal t1 transmitted from the timing control section (TC) 3 is logic "0" (step 34.
1), since the timing signal t2 is logic "1" (step 542), the number n1 of unconditional jump instructions in the current loop in the register (JCRI) 41 and the register (JC
R2) Number of unconditional jump instructions in the previous loop in 42 n2
Since both are "0", the verification signal m1 is set to logic "1" (step 5410).

As shown in FIG. 5, the jump information control unit (JDC) 5
When the timing signal t2 transmitted from the timing control section (TC) 3 is set to logic "1" (step 551), jump information jd (E-D ) and the accumulated contents of the previous condition jump information register (JDR) 51, and since they do not match, the verification signal m2 is set to logic "0" (step 553), the verification signal ml is set to logic "1", Verification signal m2 is logic “0”
Since gate 7 is set to timing control section (
When the verification signal m3 transmitted to the timing controller (TC) 3 is set to logic "0", the timing control section (TC) 3 sets the evening timing signal t4 to logic "1" (step 535).

A jump counting control unit (JCC) 4 receives a timing signal t.
3 is logic “0” and timing signal t4 is logic “1”.
” (steps S45 and 546), the number of unconditional jump instructions in the current loop n1=rOJ in the register (JCRl) 41 is set as the number of unconditional jump instructions in the previous loop n2 to register (JCR2>'4.2). In step 547), the register (JCRl) 41 is
0'' (step 848).

A jump information control unit (JDC) 5 receives a timing signal t.
4 is logic "1", the transmitted jump information jd (ED) is stored in the register (J'DR') 51 as the previous conditional jump information (step 555).

As shown in FIG. 6, the memory control unit (MMC) 5 receives the timing signal t transmitted from the timing control unit (TC) 3.
1 and t3 are both logic "0", and the timing signal t4
is logic “1” (steps S61 to S
6'3), jump information jd (E-D) transmitted from the jump instruction detection unit (JPC) 2 is stored in the memory (
MEM) 1, jump information storage address al-rlJ stored in register (JDPR) 61 (step 564), loop number storage address register (
LCPR) 62 is stored in the loop count storage address a2, and the jump information storage address a1. = “1”
In step S6'5, add "1" to "2".
), memory (MEM) 1 loop count storage address a
Step 566) to store the loop count n3 = "1" in 2'-r2J, and add "2" to the jump information storage address al-rlJ in the register (JI) PR) 61.
3" (step 567).

Next, when the unconditional jump instruction JA is detected in step S6 (FIG. 8), the jump instruction detection section (JPC)
2 sets only the jump instruction detection signal jpl to logic "1" and outputs jump information jd(F-A>).
- The timing control and control unit (TC) 3 sets the jump instruction detection signal jpl to logic "1" (step 531),
When the jump instruction detection signal jp2 is set to logic "0" (step 532), the timing signal t1 is set to logic "1" (step 536).

The jump counting control unit (JCC) 4 determines whether the timing signal t1 transmitted from the timing control unit (TC) 3 is logical “
1” (step 541), register (J
CRI) Number of unconditional jump instructions in the current loop in 41 nl
Add “1” to −40J to make “1” (Step 5
49).

The memory control unit (MMC) 6 includes a timing control unit (TC).
Since the timing signal tl transmitted from ) 3 is logic "1" (step 561), jump information jd (F
-A) in memory (MEM) 1, register (JDPR)
) 61, the jump information storage address al
- Store in r3J (step 36B), register (JD
PR) Change the jump information storage address al=r3J stored in 61 to "4" (step 569)
.

Similarly, when unconditional jump instructions JB and JC are detected in steps S8 and 510 (FIG. 8), the number of unconditional jump instructions in the current loop n1-rlJ in register (JCRI) 4.1 becomes "3". modified, memory (M
Jump information storage address a 1-r4j and "5" of EM) l Jump information jd (H-B) and jd
(GC) is stored in register (, JDPR) 61
The jump information storage address al-r5J in is changed to "6".

The second iterative process starts from step S2 (FIG. 8), and again in step S4, the conditional jump instruction J
When X is detected, the jump count control unit (JCC) 4 reads the number n1 of unconditional jump instructions in the current loop in the register (JCRI) and the number 02 of unconditional jump instructions in the previous loop in the register (JCR2). Check step 543)
, the verification signal m1 is set to logic "0" (step 544), and the jump information control unit (J
DC) 5 receives the jump information jd (E-D) transmitted from the jump instruction detection unit (JPC) 2 and the register (JPC) 5.
DR) 51 and the previous condition jump information @jd(E-D), and since they match, the verification signal m2 is set to logic “l”.
(step 856).

As a result, the timing control section (TC) 3 sets the timing signal t4 to logic "1", so the jump counting control section (TC) 3 sets the timing signal t4 to logic "1".
JCC) 4 is the number of unconditional jump instructions in the current loop in the register 41, n 1-r3J, which is stored in the register (JCR2) 42 as the number of unconditional jump instructions in the previous loop, 02, and the register (JCRl) 41 is set to "0". Initial setting steps S47 and 54B), jump information control section (
JDC) 5 stores the jump information jd (E-D) transmitted from the jump instruction detection unit (JPC) 2 in the previous condition jump information register (JDR) 51 (step 5).
55).

The memory control unit (MMC) 6 has a jump instruction detection unit (JP
C) The jump information jd (E-D) transmitted from 2 is stored in the jump information storage address al-r6J stored in the register (JDPR) 61 of the memory (MEM) 1. )'6
Loop count storage address a 2 = stored in 2
Jump r2J information storage address a 1-r6J
+ Change to Ill step 565), store the loop number n3-rlJ in the loop number storage address a2-r7J step 566), register (JDPR) 61
"2" is added to the jump information storage address al-r6J in "8" (step 567).

Thereafter, when unconditional jump instructions JA to JC are detected again in steps S6, S8, and 510 (FIG. 8), the register (JC
RI) 41 has the number of unconditional jump instructions in the current loop n1=
I3J is accumulated and jump information jd (F-A),
jd (H-B) and ja (c-, C) are memory
(MEM) 1 jump information storage address at-r8J
The jump information storage address a 1 = rl IJ is stored in the register (JDPR) 61 in the memory control unit (MMC) 6.

The third iterative process starts from step S2 (FIG. 8), and again in step S4, the conditional jump instruction J
When X is detected, the jump count control unit (JCC) 4 calculates the number of unconditional jump instructions in the current loop n 1 = r3J in the register (JCRI) and the number of unconditional jump instructions in the previous loop in the register (JCR2). Step 543) to match n2=r3J, and since they match, the matching signal m
1 to logic "1" (step 5410), and the jump information control unit (JDC) 5 receives the jump information jd(E-) transmitted from the jump command detection unit (JPC) 2.
D) and the previous conditional jump information jd (E-D) in the register (JDR) 51, and since they match, the verification signal m2 is set to logic "1" (step 553).

The gate 7 receives the verification signal m1 transmitted from the jump counting control section (JCC) 4 and the jump information control section (JDC).
Since both the verification signal m2 transmitted from the timing controller (TC) 5 is logic "1", the verification signal m3 transmitted to the timing control section (TC) 3 is set to logic "1".

The timing control unit (TC) 3 determines that the collation signal m3 is logical “
When the timing signal t3 is set to "1" (step 534), the timing signal t3 is set to logic "1" (step 537).

As a result, jump count control unit (JCC) 4 register 4
Number of unconditional jump instructions in the previous loop in 1 n2 = r3J
Register (JCRI) 41 is set to rOJ without changing
(steps S45 and 54B), and the previous condition jump information register (JDR) 51 in the jump information control unit (IDC) 5 is not changed in any way.

The memory control unit (MMC) 6 adds "1" to the loop number n3-rlJ stored in the loop number storage address a2-r7J stored in the register (LCPR) 62 of the memory (MEM) 1. (step 3610), and the jump information storage address al=rllJ stored in the register (JDPR) 61.
is changed to "8", which is obtained by adding "1" to the loop count storage address a2-r7j (step 5611).

From then on, each time steps S2 to S10 are repeated in FIG.
lJ is added.

In this way, when steps S2 to SIO in FIG. 8 are repeatedly processed 9999 times, the loop number n3 stored in the loop number storage address a2-r7J of the memory (MEM) 1 becomes r9998J, and the jump information storage address al -Jump information jd from r8J to “10”
(F-A), jd (H=B) and jd (G-C)
After is stored, when the 10,000th repetition process starts from step S2, the condition (i = l OOOO) is satisfied in step S4, resulting in jump information jd (E-END), and the number of loops is stored. "1" is stored in address a2-rl2J, and the process ends.

In the result memory (MEM) 1, as shown in FIG. 7, the jump information j of the conditional jump instruction JX detected in the first processing is stored at the jump information storage address al=r1.
d (E-D) is stored, and the jump information jd ( F-A), jd (H-
B) and jd (G-C) are stored in the jump information storage address a1=6, and the jump information jd (E-D ) is stored, and the 9999th jump information storage address al=r8J to "10" is stored.
Unconditional jump instructions JA to JC detected in the process
Jump information of jd(F-A), jd(H-B)
and jd(GC) are stored, and the jump information @jd 1-END) of the 10000th conditional jump instruction is stored in the jump information storage address a1-rl IJ, and the loop count storage address a2-2 The first loop count n3=rlJ is stored in the loop count storage address a2=r7J, the second to 9999th loop count n3=r9998J is stored in the loop count storage address a2=r12J, and the 10000th loop count is stored in the loop count storage address a2=r12J. The loop count "1" is stored and the recording ends.

As is clear from the above explanation, according to this embodiment, the eighth
The processing process shown in the figure is as shown in FIG.
It is recorded in a small storage area of EM>1 in an easy-to-understand state.

Note that FIGS. 2 to 7 are only one embodiment of the present invention, and for example, a timing control section (TC) 3, a jump counting control section (JCC) 4, a jump information control section (JDC)
5 and the memory control unit (MMC>6) are not limited to those shown in the drawings, and many other modifications may be considered; however, the effects of the present invention remain the same in any case. It goes without saying that the processing steps covered by the present invention are not limited to those shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, even when the same processing process is repeatedly executed many times in the recording device, the number of repetitions is recorded instead of repeatedly recording jump information, and the recording memory is The required storage capacity is also significantly reduced, and the information can be recorded in an easy-to-understand manner.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a recording device according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the timing control process in FIG. 2, and FIG. 4 is a diagram showing an example of the timing control process in FIG. FIG. 5 is a diagram showing an example of the jump count control process in FIG. 2; FIG. 5 is a diagram showing an example of the jump information control process in FIG. 2;
FIG. 6 is a diagram showing an example of the memory control process in FIG. 2, and FIG. In the figure, l is memory (MEM), 2 is jump instruction detection unit (JPC), and 3 is timing control unit (TC).
, 4 is jump counting control unit (JCC), 5 is jump information control unit (JDC), 6 is memory control unit (MMC)
, 7 is a gate, 41 is a register (JCRI) that stores the number n1 of unconditional jump instructions in the current loop, and 42 is a register (JCRI) that stores the number n2 of unconditional jump instructions in the previous loop.
CR2), 51 is the previous condition jump information register (JD
R), 61 is a register (JDPR) that stores jump information storage address a1, 62 is a register (LCPR) that stores loop count storage address a2, 1 is an instruction,
JA to JC are unconditional jump instructions, a is address, j
d is jump information, jpl and jp2 are jump command detection signals, ml to m3 are verification signals, n3 is the number of loops, tl to t4 are timing signals, E, F, G and H
is the jump source address, A, , B, C, and D are the jump destination addresses, steps S1 to 5610 are the steps,
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Claims (1)

[Scope of Claims] A device for recording a processing process using jump information indicating a jump source address and a jump destination address when a jump instruction is executed, comprising: identifying a jump instruction executed in the processing process and a jump condition; a jump instruction detection means (100) that outputs information (jd); and the jump information (jd) that is output when the jump instruction detection means (100) detects a conditional jump instruction.
jump information control means (200
), and jump counting control for counting and accumulating the number of unconditional jump instructions detected between two conditional jump instructions successively detected by the jump instruction detection means (100), and comparing the number with the number of unconditional jump instructions to be counted next time. When the comparison results of the means (300) and the jump information control means (200) indicate a match, and the comparison result of the jump count control means (300) indicates a match, the number of repetitions is counted and the memory ( 1) A jump history recording method characterized in that a memory control means (400) for storing data is provided.