JPH02304654A - Error detecting and correcting circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of an information processing system having an error detecting and correcting circuit by adding an inhibiting circuit for the error detection and correction to every area of a storage device so that the error detection and correction can be inhibited in an area in which the error detection and correction are unnecessary. CONSTITUTION:A register 61 in an error detecting and correcting circuit 60 corresponds to each divided area of an area of a storage device 50, and in a register corresponding to an area for inhibiting the error detection and correction by a register contents setting instruction from a CPU 10, an H level is stored. Also, a decoder 62 inputs an address signal 70 from the CPU 10, decides to which area of the device 50 the transfer is executed, and sets a flag corresponding to the area to which the transfer is executed to an H level. Subsequently, in accordance with an L level or an H level of an output of the register 61 corresponding to the flag of an H level of the decoder 62, an error detection/correction inhibiting signal 66 becomes an L level or an H level, and data outputted from the CPU 10 is inputted to the device 50 through an error detection inhibiting circuit 30 or without passing through its circuit. In such a way, the throughput of the information processing system having the circuit 30 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an erroneous detection and correction circuit, and particularly to an error detection and correction circuit that employs erroneous detection and correction suppressing means.

[Conventional technology]

In the information processing system in which the error detection and correction circuit 30 is provided between the CPt 110 and the storage device 50 as shown in FIG. 2, when CPolo writes data to the storage device 50,
input to the false detection correction circuit 30 via the transmission line 20,
A check bit is generated in the circuit. The data and check bits are then written to the storage device via transmission line 40.

When CPtJl 0 reads data from the storage device 50, the storage device 50 outputs the data and the corresponding check bit to the error detection and correction circuit SOK via the transmission path 40. The error detection and correction circuit 30 generates a check bit again based on the input data, and compares it with the check bit input from the storage device 50. As a result of the comparison, when there is a 1-bit error, the error detection and correction circuit JII50 performs the following:
Detects errors and transfers the corrected data to CPt310,
Also, the corrected data and check bits are stored in the storage device 50.
write to. If there is a 2-bit error, the error is detected and transferred to the CPU.

FIG. 5 shows the configuration of a conventional g4 detection and correction circuit. R11G31 is a register that holds read data and check bits from a storage device (not shown);
G52 indicates a register that temporarily holds data read from the storage device and data written at the time of writing.

Regarding the conventional error correction detection method,
For example, there is Japanese Patent Application Laid-Open No. 61-290541.

[Problem to be solved by the invention]

Since an information processing system equipped with an erroneous error detection and correction circuit performs the above-mentioned process, it is inevitable that the cPu cycle time will be longer than an information processing system that does not have an erroneous error detection and correction circuit.

Information processing systems equipped with conventional error detection and correction circuits are
All data, including data that does not require erroneous detection and correction, is transferred between the CPU and the storage device via the vA detection and correction circuit.
There was a problem with a decline in processing capacity.

An object of the present invention is to improve the processing capacity of an information processing system equipped with an error detection and correction circuit.

[Means to solve the problem]

In order to achieve the above purpose, a circuit to suppress erroneous detection and correction is added to each area of the storage device, and it is possible to suppress erroneous detection and correction in areas where error detection and correction is unnecessary. .

[Effect]

By providing an erroneous detection/correction suppression circuit, areas of the storage device where erroneous detection/correction is not necessary can be
Suppression of error detection and correction becomes possible, and the area where error detection and correction is suppressed during transfer with the CPU has a shorter CPLI cycle time than the area where error detection and correction is performed, and the entire information processing system The processing capacity of the system will be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The information processing system according to the present invention is CPU1a.

Erroneous detection and correction circuit 30, storage device 50. It is composed of an error detection and correction circuit 60.

The error detection and correction circuit 6a is a circuit that divides the entire area of the storage device 50 into eight areas according to addresses, and suppresses the error detection and correction function for each of the divided areas. 61. Decoder 62. Selector 65. AND circuit 64. It is composed of an OR circuit 65.

The register 61 corresponds to eight divided areas of the storage device 50, and the contents of the register are CPol.
C
The H level is stored in the register corresponding to the area where error detection and correction is suppressed by the register content setting command from Polo.

Further, the contents of the register are changed only by a register contents setting command from CPolo. The decoder 62 is a CPL
This is a circuit that inputs the address signal 70 output by the CPU 10 during transfer between llo and the storage device 50, and determines to which area of the storage device 50 crtzo transfers. The 7 lags corresponding to the 8 divided areas of the storage device 50 where the process is to be performed are set to H level.

The H level flag of the decoder 62 and the output of the register 61 corresponding to the flag are input to the selector 63 as an error detection and correction suppression signal 66 via an AND circuit 64 and an OR circuit 65. Furthermore, CPLllo) data is input to the selector 63 via a data transmission line 69. When the output of the register 61 corresponding to the flag at H level of the decoder 62 is at L level, the error detection and correction suppression signal 66 is at L level, and the data outputted by the CPU is transferred to the transmission line 68. storage device 50 via 30
is input to. Furthermore, when the output of the register 61 corresponding to the flag of the decoder 62 that has become H level is at H level,
The erroneous detection and correction suppression signal 66 becomes H level, and the CPLI
The data outputted by 10 is sent to the storage device 5 via the transmission path 67.
Input to 0.

According to this embodiment, when the CPU 10 performs transfer to an area of the storage device 50 where the error detection and correction function is suppressed,
The cycle time of CPtJlo becomes shorter. Therefore, the processing capacity of the entire information processing system is improved.

〔Effect of the invention〕

According to the present invention, c
When the pu transfers data to an area where the error detection and correction function of the storage device is suppressed, the cycle time of the CPU is shortened9, and the processing capacity of the entire information processing system is improved.

[Brief explanation of the drawing]

The first factor is a system configuration diagram of an embodiment of the present invention, FIG. 2 is a conventional system configuration diagram, and FIG. 3 is a configuration diagram of another conventional error detection and correction circuit. 10...CP[J, 30...False detection correction circuit, 50...Storage device% 60...
...Error detection and correction suppression circuit, 61...Register, 62...Decoder, 63...Selector, 66...Error detection and correction suppression signal. Nu20 Nu5 Go to figure CPLI

Claims (1)

[Claims] 1. By adding a check bit to data and storing it in a storage device, obtaining a new check bit for the data with the check bit read from the storage device, and comparing it with the read check bit, An error detection and correction circuit capable of detecting and correcting errors in data is characterized in that the entire area of a storage device is divided into a plurality of areas, and each of the divided areas is provided with means for inhibiting an error detection and correction function. error detection and correction circuit.