JPS6022253A - State record storage device - Google Patents

Abstract

PURPOSE:To use effectively a storage means by returning an address value stored at a point of time in advance to the 1st address register storing a record data at a proper point of time to delete the record data in a proper range so far. CONSTITUTION:The record data of an information processing unit 1 of an information record storage device is stored in a storage section 2, to which the storage location of a trace data is indicated by the 1st address register 3. Further, an output data of the register 3 is incremented by ''1'' by an adder 4 and an output of the adder 4 is stored in the 2nd address register 5. The output of the adder 4 and the register 5 is fed to a selection circuit 6 and a microinstruction from the processor 1 is fed to a selection circuit 6 and registers 3, 5 via a control circuit 7. Then an address value stored at a point of time is returned again to the storage section 2 at a proper point of time, the record data of a proper range is deleted to use effectively the storage section 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a state history storage device that uses an information processing device as a subject of state history investigation.

[Description of prior art]

Conventionally, in information processing equipment, when a hardware failure occurs, a history of internal state changes within the information processing equipment up to the time of failure is kept and used as information to investigate the cause of the failure. . Devices used for this purpose are called state history storage devices (hereinafter referred to as ``tracers''), which sequentially memorize internal states that are considered necessary for investigating the cause of a failure. It was designed to be ready when the time comes. The capacity of the ID storage unit used in the trainer is limited, and past trace data exceeding a certain limit will be rewritten by storing new trace data, so the method of sampling trace data is important.

In information processing devices using micro instructions.

Taking the example of a tracer that uses microinstruction addresses as part of the trace data, conventionally, if the same sequence of microinstruction addresses is repeated, such as in a waiting part of a microinstruction or a part where the same operation is repeated, In some cases, the tracer's memory was filled up. Also.

When tracing microinstruction addresses.

Depending on the control, it is sufficient to confirm that the sequence has reached its exit, and there is no need for trace data to remain.

Everything was traced. Therefore, the function of the tracer, which is to memorize as much past state changes as possible and which are effective in investigating the cause of a failure, may not be fulfilled.

[Detailed description of the invention]

SUMMARY OF THE INVENTION In view of the above drawbacks, an object of the present invention is to transfer a value at a certain point in time of a first address register that stores an address when storing trace data obtained from an information processing device in a storage means to a second address by a microinstruction. Save it in the register.

After the trace operation has further progressed, the address data stored in the second address register is returned to the first address register by a microinstruction,
It is an object of the present invention to provide a state history storage device that enables effective use of the storage means by deleting trace data in an appropriate range up to that point.

means for storing history data of the information processing device in a state history storage device in which an information processing device controlled by the information processing device is subjected to state history investigation;

a first address register that provides a storage location of history data to the storage means; a second address register that stores the output data of the first address register as input; and +1 addition to the output data of the first address register. with an adder that does.

a selection circuit that selects one of the output data of the adder and the output data of the second address register and stores it in the first address register; a signal to be stored in the address register of the address register, and an instruction to the selection circuit to select either the output of the second address register or the output of the adder, and the data selected by the selection circuit is stored in the first address register. The signal to be stored in the address register is
A state history storage device characterized in that it has a control circuit that sends data according to instructions from the microinstruction is obtained.

[Detailed description of the invention]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a state history storage device (i.e., a tracer) according to an embodiment of the present invention performs a state history investigation (tracing) of an information processing device 1 controlled by a microinstruction (2).
This is the subject of the following. The tracer of this embodiment includes a storage unit 2 that stores history data (trace data) of the information processing device 1, a first address register 3 that indicates the storage location of the trace data, and a first address register 3 that indicates the storage location of the trace data. An adder 4 that receives output data from the address register 3 and adds +1 to it, and a second adder that receives and holds output data from the adder 4.
and a selection circuit 6 that receives the output data of the adder 4 and the second address register 5 and selects one of them and stores it in the first address register 3. The adder 4 is added to the second address register 5 according to the instructions of the microinstruction.
It also instructs the selection circuit B to select either the adder 4 or the register 5, and stores the data selected by the selection circuit B in the first address register 6. It has a control circuit 7 that sends out a signal to cause the change.

The storage unit 2 traces the trace data sent from the information processing device 1 via the path 51 for each basic clock of the device, and is controlled so that the tracing operation is frozen in the event of a failure or the like.

Next, a trace operation when a microprogram as shown in FIG. 2 is executed will be explained. The microinstruction program of FIG. 2 has tracer control instructions in step a and step f.

The tracing operations at steps b, c, d, . The trace data of the information processing device 1 at a certain step is written to the storage location of the storage section 2 indicated by the address register 3, and at the same time, the digit of the address register 3 is incremented by 1 by the adder 4, and is passed through the path 53. and is input to the selection circuit 6. The selection circuit 6 normally selects the data sent via the path 53, and therefore:
The address register 3 (2) stores the address data incremented by 1. In this way, the trace data is sequentially stored in the storage location of the storage unit 2 indicated by the address register 6 for each step (2).

Next, the operation of the tracer in step a will be explained.

"Register 5 ← Address register 6" of the microinstruction in step a indicates that in this step, the data in address register 3 is incremented by 1 in adder 4 and then stored in register 5. Therefore, step After the operation a is completed, the trace data is written to the storage location indicated by the address register 3 in the storage unit 2, and at the same time, the address corresponding to the next storage location is stored in the register 5.

The operation of the tracer in the case where normal tracing operations are performed in steps b, c, and d and 9 conditions X are not satisfied and the process proceeds to step f will be described. After writing the trace data to the storage location of the storage unit 2 indicated by the address register 3, the microinstruction 0 address register 3←register 5'' is executed.
is sent to selection circuit B via
4 is selected and stored in the address register 3 through a path 55.

Next, we will explain the operation when moving from step f to step b (2).At this time, the address register 6 stores the address stored in step a.

That is, the address indicating the storage location where trace data was written when step b was executed last time is stored. Therefore, in the ninth step, the trace data obtained when the current step b was executed is newly written to the storage location. Similarly, for steps c and d, the current trace data is written to each previous storage location.

Furthermore, if one condition
The above operations are repeated.

In this way, by using two tracer control instructions in a microinstruction loop as shown in FIG. 2, the trace data written in the storage unit 2 before entering the loop can be You can trace loops.

After condition X is satisfied and step e (= moves to.

Normal tracing operations occur. Therefore, the trace data for the last one in the loop remains in the storage unit 2.

The microinstruction program shown in Figure 2 is an example of a loop, but even in a series of microinstruction programming sequences, when a certain point is reached, the trace data from a certain point in the past to the present is If it becomes unnecessary, by placing the two tracer control commands described above, the unnecessary part can be deleted and the capacity of the storage section 2 can be used effectively.

[Detailed description of the invention]

As explained above, the present invention stores an address value previously stored at a certain point in time at an appropriate point in time in a first address register that stores an address for storing historical data of an information processing device in a storage means. By returning the data to the first address register and deleting the previous leaf data in an appropriate range, the storage means can be effectively used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a state history storage device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a microprogram for explaining an example of a tracing operation by the device shown in FIG. 1... Information processing device, 2... Storage unit, 3... First
address register, 4... adder, 5... second address register, 6... selection circuit, 7... control circuit. Figure 1

Claims (1)

[Claims] 1. A state history investigation device that targets an information processing device controlled by microinstructions for state history investigation. 6. A device for storing history data of the information processing device, and a storage location of the history data in the storage device. a first address register that stores the output data of the first address register as input; an adder that adds +1 □ to the output data of the first address register; a selection circuit that selects one of the output data of the address register of memory 2 and stores it in the first address register; a signal to be stored in the second address register; and an instruction to the selection circuit to select either the output of the second address register or the output of the adder; 1. A state history storage device comprising: a control circuit that sends out a signal to be stored in one address register according to an instruction of the microinstruction.