JPS62119643A - System for storing history information - Google Patents

Abstract

PURPOSE:To attain sure recording of history information and to facilitate readout by dividing a history memory into blocks, recording the history information cyclically in one block until a specific condition takes place, transferring the block to the next block to record the history information when the specific condition is generated. CONSTITUTION:A recording control means 140 divides the history memory 120 into blocks and while no specific condition is generated, the history information is recorded cyclically in one block. On the other hand, when the specific condition is generated, a specific condition detection means 130 informs it to a recording control means 140. In receiving the notice, the recording control means 140 makes the next block record the history information. Until the next specific condition is generated, the history information is recorded cyclically in the said block. When the next specific condition is generated, the block is transferred to the next and the history information is recorded therein.

Description

[Detailed Description of the Invention] [Summary] When history information inside a computer system is stored in the history memory, a means for detecting the occurrence of a specific condition in the computer system is provided, and the history memory is divided into blocks. The history information is recorded cyclically within one block until a specific condition occurs, and when the specific condition occurs, the history information is recorded by moving to the next block. As a result, it is possible to reliably store each piece of history information when a specific condition occurs for each block using a small-capacity history memory, and it is also possible to easily read the history information when a desired specific condition occurs.

[Industrial application field]

The present invention relates to a history information storage method for storing history information regarding the internal state of a computer system in a history memory.

[Conventional technology]

In a computer system, as part of ■2 AS, time-series data of its internal state, that is, history information, is recorded in the history memory.
Specific conditions such as channel failure handling (/l) If a specific condition (/l) occurs, read out the history information recorded in the history memory and analyze its contents to investigate the cause of the specific condition and take countermeasures. I try to do this.

Conventionally, when storing historical information in history memory, all historical information regarding the internal state of a computer system is recorded at one rate, and when a specific condition occurs, the historical information at the time of occurrence of that specific condition is read out and its contents are I was trying to do an analysis.

[Problem that the invention seeks to solve]

As mentioned above, conventional history information storage systems record all history information regarding the internal state of a computer system at one rate. For this reason, not only is a large capacity memory required for history memory, but also because the rate of occurrence of specific conditions is generally small, there are many redundant parts in the recorded contents of history memory, and memory resources are not used effectively. There was a problem. Furthermore, there is a problem in that it takes time to search and read out a portion where a specific condition occurs.

By selectively recording historical information at the time when a specific condition occurs, the present invention enables to reliably record all the historical information at the time when a specific condition occurs using a small-capacity history memory, and to read out the history information at the time when a specific condition occurs. It is an object of the present invention to provide a history information storage method that can be easily performed.

[Means for solving problems]

The means taken by the present invention to solve the above-mentioned problems in the conventional history information storage system will be explained with reference to FIG.

FIG. 1 is a block diagram showing the configuration of the present invention.

In FIG. 1, 110 is a computer system, and 120 is a history memory that stores history information regarding the internal state of the computer system 110.

130 is a specific condition detection means, which is
Detects that a specific condition has occurred.

140 is a recording control means that divides the history memory 120 into blocks and records history information cyclically within one block until the specific condition occurs, and when the specific condition occurs, the record information is recorded in the next block. to record history information.

[For production]

The operation of FIG. 1 will be explained with reference to FIG. 2.

FIG. 2 is an explanatory diagram of the history information recording operation in the present invention.

The recording control means 140 divides the history memory 120 into blocks, and as long as a specific condition does not occur, the history information sent from the computer system 110 is divided into one block (first block) as shown in FIG. Therefore, the history information is repeatedly updated block by block.

On the other hand, the specific condition detection means 130
0 is checked, and when the specific condition occurs, the recording control means 140 is notified of the occurrence of the specific condition.

When the recording control means 140 receives the notification of the occurrence of this specific condition, it starts the next program (second program) as shown in FIG. 2(b).
block) to record history information. Furthermore, history information is cyclically stored in this block (second process) until the next specific condition occurs. Furthermore, when the next specific condition occurs, the program moves to the next block (third block) and records the history information. Thereafter, in the same manner, each time a new specific condition occurs, the process moves to the next block and records the history information.

As described above, each piece of history information when a specific condition occurs is stored for each block.

Therefore, it is possible to record all the historical information at the time of occurrence of a specific condition with a small memory capacity, and
By specifying the block address, history information at the time when a desired specific condition occurs can be easily read.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2-1 and 3.

FIG. 3 shows the configuration of an embodiment of the present invention. This is shown in a diagram.

(A> Configuration of the embodiment In FIG. 3, a computer system 110, a history memory 120, a specific condition detection means 130, a recording control means 1
40 is as explained in FIG.

In this embodiment, the 81 computer system 110 constitutes a microprogram controlled computer.

That is, in the computer system 110, 111 is a control memory in which microinstructions are stored. Reference numeral 112 denotes an operation register (OP register) in which microinstructions read from the control memory 111 are set. This read microinstruction is transferred to a predetermined arithmetic unit (not shown) via the data bus 113 and is also sent to the specific condition detection means 130.

In the specific condition detection means 130, reference numeral 131 denotes a condition register in which specific conditions are determined from a not-shown SVP. 132 is a comparison circuit that compares the specific condition sent from the condition register 131 and the OP register 11.
The control means 140 compares the micro-instructions sent from the micro-commands 2 and detects that a specific condition has occurred in the computer system 110 when the two match, and records a specific condition occurrence notification signal.
send to

In the recording control means 140, 141 is an addressing register, which has a segment i part (SG part) and a segment own address part (ADR part), and has a segment i part (SG part) and a segment own address part (ADR part).
An address that accesses 0 is secessed to 1-. The address of each block is set in the SG section, and the address within the valley segment is set in the ADR section, so that both are in a negative position and lower address relationship.

142 is an adder, and each time one address is output from the addressing register 41, the multiplexer 143
(via AI) Increase the address of the R section by "1".

144 is an address control circuit. In this address control circuit 144, 144a is an SG adder which adds the address of the SG section of the addressing register 41 to 11-1.
generates a summation output that increases the 144b is AD
The R adder generates an addition output that increases the address in the ADR section of the addressing register 141 by "1". 144C is an SG multiplexer which receives the SG section of the addressing register 141 and the address of the SG adder 144a, and selects the input of the SG adders 14 and 32 only when it receives a specific condition occurrence notification signal from the specific condition detection means 130. . 144d is an ADR multiplexer,
"0" is input to reset the adder 143b and the ADR section, and the input of '0' is selected only when a specific condition occurrence notification signal is received from the specific condition detection means 130.Outputs of the SG multiplexer 143C and ADR multiplexer 144d. is sent to multiplexer 143.

Reference numeral 144e denotes a recording mode setting unit, in which respective flags are set by a mode set signal supporting normal recording mode or block recording mode sent from an SVP (not shown), and a selection signal for each mode is outputted and applied to the multiplexer 143. .

In the normal recording mode, all the history information of the computer system 130 is recorded in the history memory 120 as in the conventional system. In the block recording mode, history information is recorded in units of blocks according to the present invention.

The multiplexer 143 includes a recording mode setting section 144 e
When the normal recording mode selection signal is applied from , the input from the adder 142 is selected, and when the block recording mode selection signal is applied, the input from the address control circuit 144 is selected.

(B) Operation of the Embodiment The operation of the embodiment shown in FIG. 3 will be explained separately for the normal recording mode and the block recording mode with reference to FIG.

(al) Operation in normal recording mode In the normal recording mode, the recording mode setting section 144e in the address control circuit 144 is set to the normal recording mode by SVP, and a normal recording mode selection signal is applied to the multiplexer 143.

Upon receiving this normal recording mode selection signal, multiplexer 143 selects the input from adder 142 and adds it to addressing register 141 .

As a result, the addressing register 141 increments the address of the ADR section by 1 every time it outputs one address, and every time it counts up to the block,
The G section is incremented by "1" and the next block is addressed.

As a result, all the history information sent from the computer system is recorded in the history memory 120 in the order of addresses, as in the conventional history information storage method.

Operation in block recording mode In the block recording mode, the recording mode setting section 144e is set to the block recording mode by SVP, and a block recording mode selection signal is applied to the multiplexer 143.

Upon receiving this block recording mode selection signal, multiplexer 143 selects the input from address control circuit 144 and applies it to addressing register 141 .

While the specific condition detection means 130 does not detect a specific condition, that is, while the specific condition does not occur and the specific condition occurrence notification signal is not applied from the comparison circuit 132, the SG multiplexer 14
4C selects the input from the SG section of the addressing register 141, the ADH multiplexer 144d selects the input from the ADH adder 1144b, and the multiplexer 14
3 to the addressing register 141.

In this case, the SG section of the addressing register 141 is not incremented by "1" even if the ADR section counts up by one block, but holds the address value of the SG section up to that point. The ADR section performs ADR every time one address is output.
The adder 144b increments the pulse by ``1'', and when it counts up by one block, it resets it to 0'' and repeats the operation of counting and amplifying again.

As a result, the history information sent from the computer system 110 is cyclically recorded in one block (first block) in the history recorder 120, as shown in FIG. 2(a).

Next, a specific condition occurs within the calculator system 110, and O
When the microinstruction output from the P register 112 is under a specific condition, the comparison circuit 13 of the specific condition detection means 130
2 detects the occurrence of a specific condition and sends a specific condition occurrence notification signal to the address control circuit 144.

SG multiplexer 144c of address control circuit 144
When receiving this specific condition occurrence notification signal, the SG adder 1
44a is selected, the input from the SG adder 144 is added to the SG section of the addressing register 141 via the multiplexer 143, and the address is incremented by "1". When this process is completed, the SG multiplexer 144C returns to the operation of selecting the input from the original SG section.

On the other hand, upon receiving the specific condition occurrence notification signal, the ADR multiplexer 144d of the address control circuit 144 outputs "0".
” selects the input, adds it to the ADR section of the addressing register 141 via the multiplexer 143, and resets its contents to all "0". When this process is finished, the ADR multiplexer 144d returns to the original ADH adder. The process returns to the operation of selecting the input from 144b.

As a result, the SG section of the addressing register 141 holds more addresses by "I" than before, and △l
) The R section outputs 8 l) R every time one address is output.
Adder + 44 Receiving input from b, counter I starts from “0”
-7' knob, count up 1 block, reset to "0", click 1 annozo again, j'i
<T+Repeat the work.

As a result, r of the computer system 110 before the occurrence of the specific condition
The g history information is stored in the original block (as shown in Figure 2).
1st block 11.・I) is stored in the IN after a specific condition occurs.
The information is stored in the next block (second block) as shown in Figure 2 (l).

Further, the history information is stored cyclically in this block (second block) until the next specific condition occurs.In the same way, the next block is stored every time a new specific condition occurs. Then, the history information is recorded.

In the manner described above, all the history information at the time of occurrence of each specific condition can be reliably recorded in the record 1 for each block. Note that history information immediately after the occurrence of a specific condition may be erased due to cyclic recording within a block, but the information necessary to clarify the occurrence of a specific condition is information before the occurrence of the specific condition, so in practice There are no particular problems.

Although one embodiment of the present invention has been described above, each structure of the present invention is not limited to each structure of this embodiment.

For example, instead of one type of specific condition, multiple types can be provided. In that case, a plurality of condition registers 131 are provided and each specific condition is set.

Also, instead of immediately moving to the next block when a specific condition occurs, only when a specific condition occurs, when the ADR section of the addressing register 141 counts up by one block, the SG section is set to "1". It may be made to increase. In this way, history information before and after the occurrence of the specific condition can be recorded.

G [Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(b) All historical information when specific conditions occur
It is possible to reliably record data in the Histogram memory in units of blocks.

(b) Since unnecessary history information is not recorded, Hiss 1-
In addition to being able to reduce the memory capacity, it is also possible to effectively utilize the history memory.

(c) By specifying the address of each block in the history memory, history information at the time when a desired specific condition occurs can be easily read out.

[Brief explanation of drawings]

Fig. 1: Detailed explanatory diagram of the present invention Fig. 2: Explanation of history information recording operation according to the present invention Fig. 3: An explanatory diagram of the configuration of an embodiment of the present invention . 1 and 3, 110...computer system, 120...history memory, 130...specific condition detection means, 140...recording control means.

Claims (1)

[Claims] In a history information storage method that stores history information regarding the internal state of a computer system (110) in a history memory (120), (a) detecting that a specific condition has occurred in the computer system (110); a specific condition detection means (130); (b) the history memory (120) is divided into blocks and history information is cyclically recorded in one block until the specific condition occurs; A history information storage method characterized by comprising: a recording control means (140) for moving to the next block and recording the history information.