JPS5890253A - Working history storage device - Google Patents

Abstract

PURPOSE:To ensure the quick retrieval for a fault, by providing an address producing circuit and a control circuit at a control part to use a storage circuit as a single unit or in division and collecting the history data even when the writing stop conditions of plural frequencies are satisfied. CONSTITUTION:A working history storage device consists of a control part 10 and a storage circuit 20 which is divided into plural parts. The part 10 includes an address producing circuit 11 and a control circuit 12. Furthermore the circuit 11 is provided with a mode setting circuit which decides whether the circuit 20 is used as a single unit or in division as plural circuits 21-24, an address register which designates the writing address and an arithmetic circuit. When the circuit 20 is used as a unit on the basis of the mode set by the mode setting circuit, the address of the circuit 20 is designated to write the writing data. While the writing is stopped for the storage circuits 21-24 which are under writing data with the writing started to other storage circuits 24-21 in case the circuit 20 is used in division. In such a way, the history data are collected in an easy way.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation history storage device in a data processing device T/1.

Conventionally, the operation history storage device in this type of data processing bag, 1.1ilj, is configured to stop when a predetermined stop condition is met, so it can only collect history information when the stop condition is met - times. Therefore, in the conventional device, since it is not possible to obtain information based on the stop condition that was satisfied for the third time after the 117I went out twice, there was a drawback that the amount of information when searching for a fault was small.

SUMMARY OF THE INVENTION An object of the present invention is to provide an operation history storage device that can collect operation history information for a plurality of stop 1 conditions.

According to the present invention, in the operation history storage device comprising a control unit and a memory circuit controlled by the control unit and into which internal states of a monitored device are sequentially written, the control unit includes one memory circuit. A mode setting circuit that allows you to choose whether to use it as a single unit or to divide it into multiple units.

When the memory circuit is used as a single unit by receiving a signal from the mode setting circuit, an address to which the memory circuit should be written can be specified.

Further, when the memory circuit is divided into a plurality of sections and used in response to a signal from the mode setting circuit, a stop signal stops writing to the divided memory circuit currently being written. L
, and an address generation circuit capable of specifying an address to be written to in each divided memory circuit so that writing in other divided memory circuits can be started. The device is T! 7.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and (A)
(11) shows the logical configuration when operating in normal mode, and (11) when operating in split mode. In the figure, 10 is a control section, and 20 is a storage circuit. First, to explain the configuration, the control section 10 includes an address generation circuit 1
1 and a control circuit 12. The control circuit 12 further includes a stop register, shown in the figure, in which conditions can be arbitrarily set, and mainly creates the timing of the memory circuit 20, the update timing of the address register, and the like.

Figure 2 d2 Details of address generation circuit 11 and control circuit 1
FIG. In fig.

Address register 111.1121d: This is a register that holds the desired address of the memory circuit 20 in FIG. In this embodiment, it consists of 10 bits, of which the address register 112 has the upper 2 bits.

Therefore, the memory circuit 20 is divided into four parts 1-1, and one of them can be selected. The address register 111 is the lower 8 bits, and the memory circuit 20. of FIG. 1(A) is divided into four parts. In other words, the respective addresses of the memory circuits 21, 22, 23, and 24 in FIG. 1 (11) are shown.

The output of the address register 111 is set to 1 by the arithmetic circuit 116.
The result of the calculation is sent to the storage circuit 20 of FIG. Further, the result of the calculation is set in the address register 111 according to an instruction from the control circuit 12. The output of address register 112 is:

The arithmetic circuit 114 calculates the output of the gate circuit 117,
The calculation result is led to the storage circuit 20 of FIG. Further, the result of the calculation is set in the address register 112 according to an instruction from the control circuit 12.

Gate circuits 115 to 117 are +lII'J control circuit 12
A mode flip-flop 121 is a mode setting circuit for
The circuit is configured so that it outputs 1 when the duality of "stops depending on the value of" is established, or carries out the carry output of the arithmetic circuit 116.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

The case where (mode flip-flop!=0) will be explained.

Data collected from each part of the monitored device.

The information is stored in the storage circuit 20 according to instructions from the control unit 10. The control circuit 12 in the control unit 1D selects "l" of the storage circuit 20 based on a predetermined timing. A pulse is generated and sent to the memory circuit 20. Furthermore, if the stop condition of the stop condition register (not shown) in the control circuit 12 is satisfied, the memory circuit 20
0 Stop staying in.

The mode flip-flop 121 in FIG. 2 can be arbitrarily set and is 0 in the normal mode.

When mode flip-flop 121 is 0, the carry output of arithmetic circuit 116 and the output of address register 112 are added, and address registers 111 and 112 are used in conjunction. Therefore, in the case of this embodiment, it is normal mode.
: , address register kl: 10 bits, first
As shown in Figure (A), 1024 words of the memory circuit 20 are used consecutively. The stop condition is set such that the stop occurs due to occurrence of a failure or the like. At this time, if the 0 condition for stopping is satisfied within 1024 words after starting writing, the operation status can be collected by going back to the past for the written word, and the stopping condition is satisfied after 1024 words. In this case, if you go back 1024 words and collect the operating state, you will get 7. Therefore.

When the stop condition is met for 1024 words or more.

Starting from word day 1025, the previously stored operating state is erased and the new operating state is stored at word 111. It's getting absorbed.

In this way, to know the operating status of the monitored device.

It is not very important what operating state is stored at which address in the memory circuit 12.

It is only necessary to know in what order the operating states were stored. However, when such historical data is required, it is a complicated problem, and data from various angles is required1.Therefore, the division mode of the present invention will be explained.

Switching to the split mode is performed by setting the arbitrarily settable mode flip-flop 121 to 1. When the mode flip-flop 121 is set to 1, it is determined that the 4th row up output of the arithmetic circuit 113 is added to the address register 112. Also address register 11
2, 1 is added when the stop condition is satisfied.

Therefore, the memory circuit 20 in FIG. 1(Δ) is
As shown in FIG. 1, the appropriate size can be written as 1 for which the stop 1-condition is satisfied for one of the divided memory circuits 21, 22, 23, and 24. For example, if a stop condition is satisfied during writing to the memory circuit 21, the first expansion operation of the memory circuit 22 is started, and so on. At this time, memory circuit 2
2-114. Address 1. Memory circuit 21
This is the address next to the address where the 411-include is stopped.

Although not shown in the figure, in the 1-division mode, a 4-inclusive pulse is sent from the control circuit 12 in the control unit 10 to the memory circuit 20, and even if the stop condition is met, the stop 1 knee does not occur and the division is interrupted. 1, all memory circuits 21 to '24 stopped.
It is designed to be stopped easily.

In this way, in the divided mode, the 1024-word memory circuit 20 of FIG. 1(A) is divided into four parts as shown in FIG. 1(r3), and the write stop condition is satisfied four times for each maximum of 256 words. It becomes possible to collect historical data from time to time.

As explained above, according to the present invention, the memory circuit is
When used as one or divided into one, but divided into five, it becomes possible to collect historical data when the conditions are met, which makes it possible to collect historical data when the conditions are satisfied, and when searching for faults. This has the effect of being able to obtain more collected data and quickly and easily finding faults.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing part of the address generation circuit and control circuit in the control section shown in FIG. 1. Explanation of symbols = 10 is a control unit, 11 is an address generation circuit,
12 is a control circuit, 20, 21, 22, 23.24 is a memory circuit, 111, 112 is an address register,
113° 114 is an arithmetic circuit, 115. N6,117
is a gate circuit. Reference numeral 121 designates mode flip-flops.

Claims (1)

[Scope of Claims] 1. An operation history storage device comprising a control section and a storage circuit that is controlled by the control section and in which the internal state of a monitored device is sequentially written. The control section includes a mode setting circuit that can select whether to use the storage circuit as one unit or to divide it into multiple units, and a mode setting circuit that can select whether to use the storage circuit as one unit or divide it into multiple units; When used as a device, the address to be written in the memory circuit can be specified, and when the memory circuit is divided into multiple sections in response to a signal from the mode setting circuit, a stop signal can be used to specify the address to be written into. an address generation circuit capable of specifying an address to be written to in each of the divided memory circuits so as to stop writing in the divided memory circuit and start writing in other divided memory circuits; An operation history storage device comprising: