JPH02138650A - Bus tracer - Google Patents

Abstract

PURPOSE:To collect data in many times regardless of the time required between triggers by selecting a signal causing a trigger out of those signals that are inputted from outside and may cause various triggers and setting a collection range of the trace information to the triggers. CONSTITUTION:A data transfer part 30 transfers the data set in a trace range to a trigger point pointed by the trace range pointing signal put on a signal line 52 to a secondary trace memory 110 from a trace memory 100 after the trigger signal is activated on a signal line 53. In this case, the address stored in the memory 101 storing the trace data is controlled by a memory address control part 40. Thus these operations can be freely repeated as long as the memory capacity of the memory 110 can afford.

Description

[Detailed description of the invention] (Industrial application field) BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bus tracers, and more particularly to improvements thereof.

(Prior art) Conventionally, in this type of bus tracer, data on the target bus is stored in a trace memory in synchronization with the operating clock signal of the core bus, that is, the bus clock, and the operation is stopped by a stop signal. I was observing the history on the bus.

Therefore, after data is written to the last word of the trace memory, the data is written again to the address where it was first written, and the maximum trace time depends on the capacity of the trace memory. .

In addition, when investigating data changes on the bus in response to changes in the signal that causes the trigger, start the bus trace by setting the trace stop signal on that signal in advance, and stop the trace when the trigger signal becomes active. I was investigating the trace results. If you continue to investigate, your friend will be configured to start the bus trace again.

(Problems to be Solved by the Invention) In the conventional bus tracer described above, the bus was traced without regard to signals other than the bus clock and the trace stop signal. Therefore, signals other than the two interrelated notes mentioned above traced the bus. There is a drawback in that when it becomes necessary to trace the traces and determine the correspondence between the trace results, it is necessary to investigate the trace contents by one person.

Furthermore, if there are a plurality of target trigger points and their occurrence interval is longer than the maximum trace time limited by the capacity of the trace memory, there is a drawback that it is impossible to trace at once.

An object of the present invention is to select all trigger signals caused by multiple triggers according to an external instruction, and to transfer trace data in the range specified from the outside from the upper trace memory to the sub-trace memory using this trigger signal. The above disadvantages are eliminated by allocating storage addresses for stored data.
It is an object of the present invention to provide a bus tracer configured to enable easy and reliable tracing.

(Rounding means for determining task gold tiles) The bus tracer according to the present invention includes a trace memory, a bus tracer control section, a trigger selection section, a sub-trace memory, a data transfer section, and a storage address management section. This is what I did.

The trace memory is for tracing and storing data on the bus in synchronization with the bus clock.

The bus tracer control unit is for stopping the trace operation by a stop signal and observing the history of data on the bus.

The trigger selection section is used to select all one of the trigger signals that cause a plurality of triggers based on instructions from the outside.

The trace memory is for storing data in a specified range from the trace memory in response to a specified trigger signal.

The data transfer unit is for transferring nine ranges of data instructed from the trace memory to the sub-trace memory.

The storage address management unit is for allocating a storage address for transferred data.

(Example] Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bus tracer according to the present invention.

In FIG. 1, 10 is a bus tracer control unit, 20 is a trigger select unit, 30 is a data transfer unit, 40 is a storage address management unit, 100 is a trace memory, 110 is a sub trace memory, 200 is a bus, and 300 is a bus trace. Department,
400 is a bus tracer.

In the first factor, the bus tracer 400 is a bus tracer 300 similar to the conventional bus tracer 300 configured by a bus tracer control section 10 and a trace memory 100;
0, a data transfer section 30, a storage address management section 40, and a sub trace memory 110. Bus tracer 400 is connected to bus 200 and bus 200'
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- A trigger factor signal line IP50 for carrying a trigger factor and a trigger select signal line 51 are connected to the trigger select section 20, and a trace range instruction signal line 52 is connected to the data transfer section 30.

The operation of the bus tracer 400 configured as described above is as follows.

Normally, the bus trace section 300 performs the /<s)L/-ss operation. At this time, if it is necessary to perform bus tracing by using one of the trigger factor signal line groups 50 connected to the trigger select section 20 as a trigger, the trigger select section 20 selects a trigger from among the trigger factor signal line group 50. The trigger factor on the signal line designated by the select signal line 51 is selected and sent to the data transfer unit 30 via the trigger signal line 53'57.

When the trigger signal on the signal line 53 becomes active, the data transfer unit 30 transfers the trace range booter and trace memo I71 On to the sub trace memory 1 corresponding to the trigger point designated by the trace range instruction signal on the signal line 52.
Transfer to 10. At this time, the address in the sub trace memory 110 that stores the trace data is managed by the storage address management unit 40, and the address in the sub trace memory 110 is
The same operation t- can be repeated as many times as the storage capacity of 0 allows.

(Effects of the Invention) As described above, the present invention selects a signal that is a trigger factor from among signals that are input from the outside and has a possibility of becoming a stray trigger factor, and selects a signal that is a trigger factor from among signals that are input from the outside and that has the possibility of becoming a trigger factor, and collects trace information for the trigger within a range of 14. This has the effect that any range of bus states can be traced using any signal t as a trigger, and data can be collected as many times as the capacity of the sub-trace memory allows, regardless of the time between triggers. be.

[Brief explanation of the drawing]

FIG. 1 shows a bus according to the invention. FIG. 3 is a block diagram showing the flow side. 10... Bus tracer control section 20...Trigger select section 30...Data transfer section 40...Storage address management section 100...Trace memory 110...Sub trace memory 200...ノ(su) 3()O...Bass trace part 400...Bus tracer 50-53...Signal line One of tracers

Claims (1)

[Claims] a trace memory for tracing and storing data on the bus in synchronization with a bus clock; and a bus tracer control unit for stopping the trace operation in response to a stop signal and observing the history of data on the bus. , a trigger select section for selecting one of the trigger signals that causes a plurality of triggers according to an external instruction, and a sub-trace memory for storing a range of data specified from the trace memory by the specified trigger signal. and a data transfer unit for transferring data in the specified range from the trace memory to the sub-trace memory, and a storage address management unit for assigning a storage address for the transferred data. A bust tracer that is characterized by: