JPS60204078A - Automatic logic design system - Google Patents

Abstract

PURPOSE:To perform automatically logic design by asigning equally flip flops for control which manage the state of a data structure and grasping a function to be realized as a flow of data in a principal data structure and gathering turn-on/off conditions of said flip flops to expand them in a pool system. CONSTITUTION:A syntactical analysis part 130 expands structure descriptions and operation descriptions, which are read in by an input part 120, to a structure description table 200 and an operation description table 300. A logic generating part 140 generates a control FF table 500 where flip flops for control are assigned to registers in accordance with the contents of an operation editing table 400 where contents of the operation description table 300 are edited. A control signal table 600 is generated where peculiar control signals are assigned to registers, memories, etc. registered in a structure storage table 200. A list table of control logics is generated as a control logic table 700 and is outputted by an output part 150.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an automatic logic design system for performing logic design of a digital logic system using a computer.

[Background of the Invention] ' Generally, two computers are designed through the following stages: system design, logic design, implementation design, and adjustment. In recent years, the stage after implementation design has been ODA (1) esjgnAutomati
on) Advances in technology have led to significant automation.

At the formal design and logic design stages, attempts are being made to improve the method and automate the design, but still...
It requires a large amount of man-hours, and the design period typically takes years, especially for large computers.

Furthermore, with recent advances in semiconductor technology, VLSI (or UL8I) with a large number of built-in gates has appeared, but a logic design method that effectively utilizes such advances in semiconductor technology has not been established.

[Purpose of the invention]

In view of the above-mentioned current situation, an object of the present invention is to provide an automatic logic design system that automatically performs logic design using a computer and reduces the number of design steps at the science and design stage. The logic designer selects the functions to be realized in the system to be designed, and then determines a rough block diagram for realizing all of these functions. Then, in the early stages of refining the method of realizing functions while taking various constraints into consideration, the block diagram that is determined does not contain detailed control logic, but registers, etc.
Memories, selectors, or connection information between them, etc.
The main data structures required to implement the desired functionality are represented in the table below.Therefore, they are assigned to control flip and flow rules for managing the state of these main data structures, and then , by considering the function to be realized as the flow of data within the above main data structure, the on10ff of the control clip frog
It is characterized by collecting conditions and expanding these ON and 10ff conditions into a pool type, which becomes the control logic necessary for the system to be designed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram of a logical system 1 (having a memory) to be designed, and its outline is as follows.

There are 2 boats as inputs. Each boat has an address INA.
(0) 10, INA(1)11, write data IND(0)20. IND(1) has 21.

There is one output port, and the read data is 0UTD40.

- Internal registers (AOREG12, AIREG13, D
OREG22. There is a DiREG 231, which is connected to an address register (A2REG) 15 and a gater register +D2REG) 25 provided for accessing the memory (MEM30) via a selector T5ELAI4.5RLD14). In addition, memory (
The data read from MEM) 30 is set to -H in the data register (D3REG) 35 and then becomes 0UTD.
40.

Now, this automatic logic design system that completely automatically designs the logic system 1 will be explained. Basically, this automatic logic design system inputs the internal data structure (registers, etc.), the functional form (logical operation of the system), and calculates the logic necessary to control the internal data structure (registers, etc.).
(referred to as control logic).

FIG. 2 is a block diagram showing the concept of an automatic logic design system. The automatic logic design system can be broadly divided into an input section 120. Syntax analysis unit 130, logic generation unit 140, output unit 150 and 6s tables, ie, structure description table 200, behavior description table 300, behavior editing table 400. Control FF table 500° Control signal table 600. It consists of a control logic table 700.

The input unit 120 inputs a data structure (of a logical system to be designed) written in a hardware description language having predetermined syntax rules (a part that declares registers, memory, etc.), and a structure description. ) and
A functional form (indicating how data flows between registers and memories in the internal structure...referred to as a behavioral description) is read from the keyboard 110 or external storage 115. Structural descriptions and behavioral descriptions are stored in the external storage 115 in advance.

The syntax analysis unit 130 reads fc in the input unit 120.
, is a part that analyzes the structural description/behavioral description according to syntax rules, and expands it into a structural description table 200 and a behavioral description table 300 for convenience in later processing.

The structural description table 200 and behavioral description table 300 created by the logic generation unit 140f''s and the syntactic analysis unit 130 are input, and the following four steps of processing are performed.

First step: A behavior editing table 400 is created by editing the contents of the behavior description table 300.

Second stage: From the contents of the structure description table 200 and the above-mentioned operation editing table 400, the control flip and
A control FF table 500 to which flops are allocated is created. The control logic for turning on and off the control FF is the object of generation.

Third stage: A control signal specific to each register, memory, etc. registered in the structure description table 200 (a set signal for a register, a write permission signal for a memory)
A control signal table 600 is created in which the control signals (WE, etc.) are assigned. The control logic that turns on and off these control signals is the target of generation. Fourth stage: A list table of the control logic that is the target of generation as described in the second stage or the third stage is set as the control logic table 700. In the 0 output unit 150 that creates 1,
The input structure description, the control FF allocated by the logic generation unit 140, or the generated control logic are output to a detailed logic description file and displayed on the display 160 as a logic port.

Detailed specifications and specific processing methods for each table will be explained below.

FIG. 10 is a flowchart showing an example of the processing procedure of the automatic logic design system.

First, the data structure (structural description) and functional format (behavioral description) of the logical system are input using the hardware description language (step 810).

Further, FIG. 3 shows a structure description table 200. Logic elements are registers, as shown in Figure 3,
Main components such as memory and selector 0 This structure description table 201j shows the connection relationship of each theory @A element ・Logic element 210 ・Signal light of element 22
0. Furthermore, it consists of a term indicating the signal light 230. For example,
The signal light of the address register (AOREG) 12 is the input capo) INA(0) 10, and is the 0-side input InO of the signal light I'X selector (SELA) 14.

In addition, the memory (MEM) 30 has an address, data in, and data out, and these are each (A2REG).
) 15, (D2R, EG) 25, (D3REG) 35, and the selector (
Since SELA) 14 has 2 inputs, ink each of them.

If inl, the signal light is sent to the address register (AORE
G)12. (AIREG) 13.

On the other hand, since the signal light is in one place, all together (A
IREG)15. Selector (SELD)
The same goes for 24 (step 820).

FIG. 4 is a diagram showing an example of a behavioral description. The result of processing this by the syntax analysis unit 130 is a behavioral description table 300 as shown in FIG.

Here, the functions to be processed by the logic system 1 (target of the automatic logic generation system) shown in FIG. 1 are the read/write (READ(0)
) 50. WRITE (0) 51) and read/write on boat 1 side (READ (1) 52, WRI T E
+1)53).

)LEAD(0)50 consists of four operation units〇(1
) If the required signal ratio DREQ, 0 is On, the input capo) I
If the data on NA(0) 10 is not stored in the address register (2) and memory (MEM) 30 is busy (coMEM-B
8Y), sets the contents of the address register (AOREGI 12) to the address register (A2REG) 15.

At the same time, the memory (MEM) 30 is activated.

(3) This description formula is a dummy cycle, during which a read operation is performed in the memory (MEM) 30. (4) Data is stored in memory (MEM) after the cycle
30. This is data.
3REG) Set to 35. During this time, it is synchronized with one pair of clocks for each 2 operation unit.

Other operations are almost the same, but WRITE (0) 51
, WRITE (1) 53, when the conditions of the if statement are satisfied, data transfer between addresses and registers and between data and registers is performed simultaneously. Furthermore, in Figure 4,
READ(1)52. WRITE (1) is "l/7'%
Fuetsu 1000 days / 7-1st - Singing elementary school 1f Smooth broom peeling IAOREG-
BSY・・・Address register (AOREG) 1
2 is not busy] 0 Now, the behavior description table 300 showing the result of analyzing the behavior description shown in FIG.
10, operation unit 320 of each operation system, operation content 330, and operation conditions 340 for each operation content.

The motion description consists of four functions to be processed (each of which is defined by motion thread 3).
10, READ (0), WRI T E (0)
.

几EAD (indicated by υ, WRITE (1)). Each operation system 310 is further classified into each operation unit 320. The contents of each operation unit 320 are divided into specific operation contents 330. The operating conditions 340 for executing this operation are stored separately (step 830). Next, the logic generation unit 140
The process is divided into four stages, and corresponding to each stage,
Each table shown in FIGS. 6 to 9 is created @ In the first stage of the logic generation unit 140, the behavioral description table 3
Based on 00, a motion editing table 400 as shown in JgJ6■ is created (step 840).

The behavior editing table 400 shows, for each logical element of the behavior content 330 that appears in the behavior description table 300 shown in Section 5, Section 1, where in the behavior description table 300 the logical element is indicated to the data receiving side of the data transfer description. This indicates whether the

Therefore, in the operation editing table 400, there is a logical element 420 storing the logical element name, and an item number 410 . assigned to each logical element 420. It consists of each item of the operation system 430 indicating the operation in which each logic element 420 is involved. The operation system 430 includes four types of operation systems EAD(0)431. WR
ITE(0)432゜EADIυ433. WRITE
lIJ434 is shown. For example, item number 4 of 6M
10, number 101, logical element 420 is AOREG, check the operation system 310 and operation unit 320'i in which data is transferred to AOREG in operation content 330 in Figure @5.

READ(0), 1 and WRI '1”E respectively
(0), 1, of the operating system 430 in FIG.
(0) 432 corresponding locations, respectively.
J k Set OHere, although the memory (MEM+301C) is not explicitly shown in the 2 behavior description table 300, from the connection relationship between the logical elements 210 shown in the structure description table 200 in FIG. It is determined which action unit corresponds to the description, and the number of this action unit is set.On the other hand, the selector +5ELA) 14, (SELD) 2
4 stores the number of the operation unit involved in the data transfer description via these selectors.

At the second stage of the logic generation unit 140, the logic element 2 in FIG.
Out of the 10 registers and memories that require state management, state control flip-flops (CFF1 are allocated. A control I'F table 500 shown in FIG. 7(a) K is created (step 850) O state control flip-flops. (OF
F) is then (1) B-bit (Busy-Bit):
Turns on when data needs to be held in the logic element 520. That is, it becomes a deterrent factor for the set condition. (2) V-bit (■alid-13itl: Becomes 011 when valid data exists in the logical element 520.

In other words, it becomes a factor for generating a data transfer request to the primary signal light (31A-bit (Affribufe-Bat):
Ff [ita
data indicating the characteristics of the logic element 520 itself and the logic element 520 itself are stored here. For simplicity, only the operation system is stored in its entirety.
1. WRITE (because there are 4 ways of IJ) A-blt is assigned to the 4 bits from the 4th bit to each register, but in reality, as shown in Figure 7 (aXb), some of them are unused. In addition, Figure 7 (a) Nioite, RO
: I(, EAD(0), Vl :Wl(I'L"E
(n1u 1! T?, RAnllll-Wl :”W
RITE (II) and slightly less than 1.

The control FF table 500 has item number 510. It consists of logical elements 520 such as register names, and sub-item numbers 530 indicating state control slip-flops.

The subitem number 530 indicating the state control flip-flop is n.
-bttsat, v-bitsa2゜A-bitsaa
consisting of numbers 01, 02, 03 of sub-item number 530, respectively.
Corresponds to ~06.

33-,,bit531. For V-bit532,
Control logic for ion-off of these control slip-flops (sub-item numbers 5300 numbers 01 to 06) is generated. The control logic is registered in a control logic table 700 (FIG. 9), which will be described later. The number indicating the registration location in this control logic table 700 is B-brt of the control FF table 500 shown in FIG. s 31-
It is stored in V-btts a 2. (Note that A-bit
is the dependent information of V-bit, so the 0n10th condition is y
- Same as bit. )Logic generation ff1s14
In the third step at step 0, a control signal table 600 (8th N) in which control signals necessary for controlling each logic element are assigned is created (step 860).

The control signal table 600 includes: Item number 61o, logic element type 620, signal name assigned to each logic element 630. Logical element pointer 64 indicating a pointer to the m-work editing table
o, control logic pointer 650, which indicates a pointer to the control logic table.

A set signal for the register is assigned to the register. For the memory (MEM) 30, a request signal (MEMREQ) for this memory IJ (MEM) 30 is sent.
) and a write enable signal (MEMWE) for distinguishing between reading and writing.'Ir is assigned.

Furthermore, selector (8ELA114.(SELD)24
For example, select signal equal to the number of input data for the selector is assigned to 0.
ELA) 14, the address register (AOREG
) 12 and (Al几EG) 13 Since there are two people, select signal 8ELA01 (EG, 8
Assign ELAIREG〇 Control logic for turning on the assigned control signal in this way is generated and registered in the control logic table 700 shown in FIG. 9, but the number indicating this registration location is shown in FIG. 8. Store the number indicating the item number 410 in the operation editing table 400 (FIG. 6) in which the logic elements corresponding to each signal are registered in the control signal table 6000 control logic pointer 650 column indicated by @. Logical element pointer 640 of table 600
In the final stage of the logic generation unit 140, control flip-flops (13-bit, ■-bit
etc.) and an on10ff condition for the control signal (register set signal, etc.) assigned to the logic element, and register the logical formula in the control logic table 700 shown in FIG. 9 (steps 870, 880). .

The control logic table 700 has ・term! 710. Control PF pointer 720 indicating a pointer to the control FF table. Control signal pointer 73 indicating a pointer to the control signal table
0. It consists of each item of the generated logical formula 740.

In the control logic table 700, the registered logic formula is the control F
If the corresponding control FF is registered, the number (item number 510 and sub-item number 530) in the control FF table 500 shown in FIG.
0, and if the registered logical expression corresponds to a control signal, the 8th one in which the corresponding control signal is registered is
The number in the control signal table 600 shown in the figure (item number 61
0) is stored in the control signal pointer 730. Logical formula 74
In the 0 column, the pool formula itself is stored as control logic. Then, in the control logic table 700, [logical formula J74
0i is output (step 89o).

Next, an example of generating control logic will be described.

(1) In the case of the V-bit setting condition of A2⇠EGI 5: (1) A2 of the operation editing table 400 shown in FIG.
If you look at the EG column (item number 103) - R of operation system 430
, EAD(0)431, WRITE(0)432.
几EAD (1) 433, WRI T E (1) 43
It can be seen that in each operation unit number "2" of 4, the address register A2REGI 5 is referenced◇ (11) Therefore, the operation description table 30 shown in FIG.
If you look at 0, it is READ (0) of the operation system 310.

The operating condition 340 indicated by the number "2" in the operating unit 320 of WRITE (0) is (MEM-BSY).

On the other hand, RE A D (1) of the operation system 310, VI I
T E (Looking at the number "2" of the operating unit 320 of 11, the operating conditions 340 are both hMEM-BAY) and (koAOREG-BSY)
It is. Here, -A21%EG15 signal light.

It is assumed that valid data exists in AOREGI 2 or A1 EGI 3, that is, each V-bit is on.

(iiD Since each operation system is an independent process, A2
几EGIsoV-bit condition f1 is as follows (AOREG-VLD and (-1MEM-BAY
) and READOI Or(AOREG-VLD and (*MEM-BS
Y) and WRITEO) or (AIREG-VLD and (koMEM-BA
Y) and (koAOREG-BSY) and READ 1) Or(AIREG-VLD and ('mMEM-E
S8Y) and (qAOREG-BSY) and W
RITEI) (1v) This logical formula is, for example, number 1 of item number 710 of the control logic table 700 shown in FIG.
If it is registered as 00, then this number is A2 of number 103 of item number 510 of control FF table 500 shown in FIG.
At the same time as writing in the V-bit 532 (sub-item number 02) of the EG15, the pointer r102-02J to the V-bit is stored in the control FF pointer 720 of the control logic table 700 shown in FIG.

(2) A2REG15cD set) conditions ('5ETA2R
EG): A2 几EGI 5 set condition is A21
V-bit of tEG15 (A 2 RE G-VL
Same as D).

Similarly, the setting conditions for A-bit (there are 4 bits) corresponding to A2REG15 are also the same.

Generally, in the case of a register, the set condition for the -V-bit is configured in the same way as the set condition for the 0B-bit, which also serves as the set condition for the corresponding register, and the control logic corresponding to control signals such as MEMREQ and MEMWE.

〔Effect of the invention〕

According to the present invention, we focus on the main data structures (registers, memories, etc.) that are essential for achieving the desired functions, and control flips that are uniformly assigned to manage the states of these data structures. Control logic for turning on and off control signals assigned to flops and data structures can be automatically generated from information indicating the flow of data between data structures, resulting in the reduction of design man-hours at the logic design stage.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of the digital logic system handled by the automatic logic generation system. Figure 2 is a diagram showing an example of the configuration of the automatic logic generation system. Figure 3 is the structure of the f'i structure description table a2. Figure 2 shows an example of the 11th masterpiece description, Figure 5 shows the specifications of the action description table 4, Figure 6 shows the specifications of the action editing table, and Figure 7 shows the control FF. Figure 8 is a diagram showing the specifications of the table; Figure 9 is a diagram showing the specifications of the control logic table; Figure 10 is a flowchart showing an example of the processing procedure of the automatic logic design system. be. 120... Input section, 130... Syntax analysis section, 140
...Logic generation section, 150... Output section, 200...
Structure description table, 300... Behavior description table 2
400...Motion editing table 500...Control F'
F table・600...Control signal table, 700・
...Control logic diagram 1 Figure σUrD Figure 2 Figure 3 TJ4 diagram +, rlr wrREat the, (AoREt
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Claims (1)

[Claims] 1. Components of the digital logic system to be designed,
In a logic design system that designs detailed control logic of the digital logic system by inputting data transfer specifications between the components, Control of the control slip-flop stored in the first table based on the data transfer specifications between the first table and the second table that stores control signals corresponding to the component. An automatic logic design system comprising: logic and means for generating control logic for turning on and off the control signal 2 stored in the second table.