JPS62109144A - Information processor - Google Patents

Abstract

PURPOSE:To produce a simple software by providing a mechanism for the control of virtual memory into a CPU and therefore attaining a memory map I/O on a virtual memory space through the CPU. CONSTITUTION:When the address conversion is carried out by a conversion index buffer mechanism 11, a signal is produced from a virtual address to discriminate the address that designates the contents of a main memory from that designates an external input/output device via a real address together with this real address corresponding to said virtual address. A control circuit uses said produced signal to supply the input/output control signals corresponding to both accesses to the main memory and the external input/output. Thus a memory map I/O is possible on a virtual memory space. Furthermore the system constitution including a CPU is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Sedentary Work Use) The present invention relates to an information processing device, and particularly to a central processing unit of the former.

(Prior art) Conventionally, a central processing unit C consisting of one semiconductor chip
The following method is generally known as a method for a CPU (hereinafter referred to as a CPU) to access an external input/output device c (hereinafter referred to as an I10 device) installed around the CPU. It transfers data between the CPU and the 110 device using the I10 device number generated by the I/O command and the read and write signals to Ilo. In response, an access method for an I10 device called Memory Mabuto I10 has been proposed. This method uses part of the address area KI1 originally reserved for main memory.
0 device address, and uses main memory addresses and main memory write and read signals generated based on main memory write and read instructions, arithmetic instructions, etc. between the CPU and the I10 device. It is used to exchange data.

A feature of the memory update I10 is that it is possible to specify the I10 device in the same way as the main memory using operands such as general arithmetic and logic operation instructions and transfer instructions.

However, the memory map Ilo has the following drawbacks.

■ Main memory and I
Although it was possible to access the device using almost the same input/output control as the No. 10 device, this is not the case with a CPU that operates at high speed with a clock frequency exceeding 8 MHz.

This is because main memory supports high-speed access.
Although all architectures such as interleaving, nibble access, page mode access, etc., can be employed, the 10th generation device inherently cannot employ such architectures. Therefore, timing control systems such as cycle time and recovery time are hardly applicable to main memory access and I10 device access. For this reason, is there a way to completely solve this problem with a CPU with a memory-mapped I10 configuration by using peripheral circuits? An extra addition is required, making the system configuration complicated.

■Memory up) CPU UH with I10 configuration, because it is basically not possible to determine internally which part of the address is connected to the I10 device, - Function to interrupt VC instruction execution when accessing the I10 device, and a function that generates an internal interrupt at that time [hereinafter referred to as the I/(JAccess2F1 function)]: - A function that allows the user to specify the privilege level at which the user wishes to access the I10 device (hereinafter referred to as the I10 special function) (This is called the certainty level specification function): It is not possible to have CP[, l inside. If all of these functions were to be realized, an additional circuit outside the j9CPU and a special interrupt processing function would be required.

(Memory map) In the I2O3 configuration, it is not possible to allocate all address space to main memory. That is, only a part of the address space can be allocated by I10100. If the I10100 address space is set larger than the I10100 address space, for example, if the most significant bit of the address is used to distinguish between the main memory and Ilo, so that both have the same size space, then the I10
Although an address decoder for identifying from the 100 memory space is unnecessary or small in size, the size of the main memory is reduced and the degree of freedom is reduced. Also, make full use of the I/(,) space, ! Most of the address space can easily be left unused.

On the other hand, if the I10 space is made smaller than the entire address space, the efficiency of use between the main memory space and l10g and the free g
is increased, but the address duplication becomes large. Moreover, in order to be able to allocate an arbitrary position in the I10100 address space, a very complicated address duder is required. That is, in the case of a 110ff memory processor, there is a trade-off relationship between the proportion of I10100 in the address space and the scale of the external address decoder, which results in an undesirable result in terms of system configuration.

(Problems to be Solved by the Present Invention) Recently, CPUs equipped with a virtual memory management mechanism have been proposed. According to this, some problems in storage management can be solved. For example, a CPU with memory Matsubuto I10 configuration
In the embodiment of virtual memory management for virtual memory space, it is possible to allocate an arbitrary part of the virtual memory space to '1I10 devices and the remaining part to the main memory, and ■I10! This has the effect of making it possible to control access rights and protect the storage space from illegal access in the same way as main memory. However, since the real address space has a memory map 10 configuration, the three problems of the memory map 10 configuration described above are not essentially solved.

Memory map) I10I? ''-In an example of virtual memory management for a CPU that does not require a lot of money, main memory access and I10 device access are judged separately within the CPU, and the function 10 access trap function and I10% privilege level specification function are implemented. However, since the real address space does not include the I10 address, the I
This method has the disadvantage that it is difficult to protect the flexible I10 device because the I10 device cannot be specified by using the command operand, and the access rights to the I10 device cannot be controlled using the virtual memory management system.

(Means for Solving the Problems) The present invention provides a mechanism for managing virtual memory inside a single-chip CPU, thereby realizing the entire memory of Matsubuto I10 in the virtual memory space of the CPU, and simplifying the software. On the other hand, the real storage space is separated into 1I10 space and the main storage space, and the corresponding CP
By determining the difference between the two spaces, U determines: - A function to suspend instruction execution when accessing the I10 device and a function to generate an internal interrupt at that time: - Privilege level at which the I10 device access is desired to be executed. A feature of the present invention is that the functions specified by the user: - The functions of generating special timing and input/output control signal for I10 device access can be realized within the CPU.

That is, the information processing device of the present invention includes a conversion index buffer mechanism for performing high-speed conversion from virtual addresses to real addresses within the central processing unit, and an input/output control signal in the central processing unit IL that performs all virtual memory management. When address translation is performed in the translation index buffer mechanism, the real address is converted from a virtual address to a real address corresponding to the virtual address, and whether the real address is a self-specified address in main memory or an external input. A signal is generated to distinguish whether the address is specified by the output device i1e, and the control circuit uses the signal to supply input/output control signals corresponding to both main memory access and external input/output access. This is what I did. In this case, the present invention is used: ■ Conversion from virtual address to real address When converting an address using the index buffer mechanism, information c indicating whether the real address is a main memory address or an external input/output address is stored. (hereinafter referred to as M/IO information).

■ Include the M/IO information in the address translation table used for virtual memory management and set its value arbitrarily.
It becomes possible to allocate the entire main memory of the remaining subspaces to any subspace sound I10 device in the virtual storage space.

■ Furthermore, by using the M/IO information inside the CPU, there is a function that interrupts instruction execution when accessing the I10 device, and a function that generates an internal interrupt at that time. Level: Functions specified by all users: 1. Function to generate special timing and input/output control signals for access of 10 devices: can be realized within the CPU.

According to the present invention, by allocating the I10 space to any partial space of the entire virtual space, the main memory reference method with abundant instructions executed by the CPU can be used also for the I10 space,
At the same time, the efficiency of program development and program debugging is impaired by interrupting instruction execution or generating internal interrupts when accessing the I10 device. Furthermore, all users can specify the privilege level they want to access the I10 device, allowing the CPU to manage external input/output devices at any level from the highest level of the operating system to the user level. . Furthermore, the I10 device uses the CPU to generate corresponding input/output control signals, thereby controlling the circuits around the CPU V! This has various excellent effects such as simple construction.

(Explanation of Examples) The present invention will be explained based on the drawings.

FIG. 1 is a block diagram of a simple embodiment of the present invention, and FIG. 2 is a block diagram of a first embodiment of the present invention.
Figure 3 is a circuit diagram of the main part of an example of an actual journey of the conversion index search mechanism, Figures 3 and 4 are diagrams showing an example of implementation at the automaton level, Figure 5
The figure shows a timing chart for main memory read access, FIG. 6h, and a timing chart for I10 device read access, respectively.

First, the functions of the valley components in each figure will be explained.

In the figure, 10 is a latch that receives the virtual address of the operand of an instruction executed by the CPU. The virtual address 21 outputted from here is translated into a real address 22 through a translation lookaside buffer mechanism C (hereinafter referred to as TLB) ll'. 11 searches the index data based on the upper data 23 of the virtual address, and if the corresponding data is found, outputs the upper data 24 of the corresponding real address and the M/IO information 25 corresponding to the real address as a conversion result. T
LB'''C.The details are shown in Figure 2.12
is an interrupt control circuit. I based on M/IO information 25
In addition to the conventional interrupt handling functions, a function is added to detect access to the I10 device and handle an interrupt when the I10 device is accessed at a privilege level other than the specified privilege level. 13 is the current C
'This register indicates the privilege level of instruction execution by the PU.

Reference numeral 14 is a register provided for the user to specify the privilege level for accessing I10. A control circuit 15 compares the contents of the registers 13 and 14, and if they do not match and an I10 access occurs, requests a full interrupt. This is a control circuit for generating an input/output control signal group 26 to be supplied to the outside of the embodiment based on the 16th M/IO information 25. The input/output control signal group 26 corresponds to the input/output control signal group shown in FIGS. 5 and 6. Details of this are shown in Figures 3 and 4. 17 is a group of real address terminals. Real BI transformed by T
The upper data 24 of the I address and the lower data 27 of the unconverted virtual address are combined to form a real address 22, which is then output. 18HM/IO signal terminal. T
The M/IOBII information 25 converted in is output from here. 19 is a group of input/output control signal terminals. The input/output control signal group 26 generated by the control circuit 12 is output from here.

FIG. 2 is a circuit diagram showing a detailed implementation BII example of T in FIG. 1. Blocks 11-1 to 11-3 indicate one entry of the TLB. The TLBU is composed of a plurality of such entries connected in cascade. 11-4 is a virtual address data register'), T
Virtual address upper data held as index data of pB is stored.

The real address data register 11-5H stores real address upper data corresponding to the address stored in the mechanical virtual address data register 11-4. Reference numeral 11-6 is an M/IO information register in which M/IO information corresponding to the address stored in the real address data register 11-5 is stored.

Reference numeral 11-7 represents a comparator, and gates 11-8, 11-9, and 11-9 for controlling the passage of Fi data, respectively.

3 and 4 show a control circuit 1 for reading data.
We will show an example of implementation at the automaton level of 2.
The figure shows the state transition in the read cycle from main memory.
FIG. 4 shows the state transitions Xt--respectively during a read cycle from an I10 device. In both figures, circles indicate the state and arrows indicate the transition gold. here,
A transition occurs every clock cycle, and the expression to the left of the diagonal line represents the transition condition when there are multiple transition destinations, and the expression to the right of the diagonal line represents the output change during the transition. The signal names appearing in the equations have the same names and meanings as those in FIGS. 5 and 6 described below. In FIGS. 5 and 6, CLK is supplied to the CPU. clock input signal to A23-AO, main memory and I
10 an address signal for accessing the device; BOY is an output signal indicating that the address signal is valid;
R, /Wl-) An output signal for distinguishing between reading and writing, an output signal indicating that the DSHCPU is in a state to receive a data signal, Data is a data input signal, fle
ady is an input signal that the main memory or I10 device notifies the end of the read process, and MRQ is an input signal that indicates the main memory access and I10
[Output signal for distinguishing location access, 5T2-0
1 (, e
Ady, MRQ, 5T2-0 The operation of the CPU that is affected by Q, which is the output control signal, will be explained.

For the virtual address calculated including index information and displacement information during instruction execution within the CPU,
The virtual address is transferred to the latch 10 when a read/input request for an instruction occurs in the operand order.

Upper value of virtual address 21 23dTI, 5xlvc%
The value 27 of the F position is transferred to the bean paste 17, respectively. 1 shift 23 transferred to TLB□1 is transferred to TLB□1.
-1 to 3)) are simultaneously compared with the value stored in the virtual address register 11-4 using the comparator 11-7. If a matching entry exists, the comparator output 11-10 in that entry is generated, thereby opening the pass control game 11-8, 11-9. the result,
The contents of the real address data register 11-5 and M/I (
The contents of the J information register 11-6 are output as the upper value 24 of the real address and the A/l/IO information 25 of the @Kio address. If there is no matching entry, based on the virtual memory management method, the three registers 11-4, 11-5, 11-
The contents of 6 are updated, and after the update is completed, re-comparison is performed.
Upper value 24 of real address and M/I of @recorded address
O information 25 is output.

Upper value 24BI of the real address output from T
I is transferred to the Zuiko group 17. The nine l'l/l/IO information 25 output from the TL8□1 is transferred to the terminal 18, and is also transmitted to the interrupt control circuit 12. Control circuit 15° is transferred to control circuit 16. If there is an instruction stop request or internal interrupt request for I10 access, the interrupt control circuit 1
2 interrupts instruction execution based on M/10 information 25. The control circuit 15 monitors the privilege level for I10 access. The current privilege level stored in register 13 and the user specified I1 stored in register 14
0 access privilege level and if they do not match, an I10 access request occurs, and the M/IQ information 25 indicates 110 access, the control circuit 15 sends a signal to the interrupt control circuit 2 to request access privilege level. request interrupt processing.

The control circuit 12 generates input/output control signals based on the M/IO1 report 25.

Now, assuming that the CPU performs an access to read data and audio from the outside, if the M/IO information 25 indicates access to the main memory, a human output control signal is generated according to the automaton shown in FIG.

3 in Figure 3, when the CPU is in the initial state SO, AIQ1
When the signal becomes logical 0, the CPU shifts to state S1 at the next clock, and shifts to state S2 at the second clock when the BCY polarity and DS1g are set to zero.

If the READY signal sent from the main memory is logic 1, the CPU waits for a response (IAL) When the Yim signal becomes logic 0, it transitions to state S3, and at the next clock
Raise the signal and DS Gogo to cooking 1 and transition to the initial state So. As a result of these operations, a signal response as shown in the timing chart of FIG. 5 occurs.

If the M/IO information 25 indicates access by the I10 device, the automaton Vc in FIG.
A number is generated. The difference between the state transitions in FIG. 4 and FIG. 3 is that by placing state Si between state S and state SR, the signal from the I10 device can be read in a sufficiently stable state. It is. In addition, in an embodiment different from this embodiment, in consideration of the fact that the fl, 110% position requires more time for address decoding than the main memory, DS is performed between state Sl and state Si. Inversion of the signal from state Si to state S! The operation result of the automaton shown in FIG. 4 for the non-example, in which the selection of the I10 device is made with full margin, is as shown in FIG. 6.

In this embodiment, all N/IO information is used: - I10 access trap function φ I10 special level specification function; - I10 access human output control signal generation function; How to protect virtual memory management fj! : It is also possible to change.

(Effects of the Invention) As described above, the present invention enables memory mapping (Ilo) to be performed on the virtual memory space by simply adding a few control circuits to the conventional virtual memory management mechanism, and simplifies the system configuration including the CPU. Furthermore, the functions of the CPU can be greatly increased.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing all 11 in Fig. 1 in more detail, and Figs. 3 and 4 are 12 automaton levels shown in Fig. 1. It is a diagram showing an example of implementation. 10...Virtual address latch, 11...
-Translation index search mechanism (TLB), 12... Interrupt control circuit. 13... Privilege level display register, 14...
...I10 access level register, 15...
・I10 access level monitoring circuit, 16...Input/output control signal generation circuit, 17...Fu address terminal group, 1B...M/IO address terminal, 19...・
...I/O control signal terminal group, 11-1.11-2.1
1-3...Each two/tri in TLB, 11-
4...Virtual address data register, 11-5
...Real address data register, 11-6...
...M/IO information register, 11-7...T
A comparator for detecting whether the data input to LB and the contents of the virtual address data register 11-4 match by comparing ML, 11-8°11-9... Comparator 11-7 Gate %11-10 determines whether or not to pass data according to the output of the comparator 11-7. It shows address signals, data signals, and input/output control signals. Figure 5 is a time chart for excluding read access from main memory, and Figure 6 is a time chart for read access from an I/C device. It is a chart. Provided for CLKflCPU! A23-AO is an address signal for accessing the main memory and I10 device, BCYI-j is an output signal indicating that the above address signal is valid, 1(, /W distinguishes between reading and writing. Output signal for L) S fl
An output signal indicating that the CPU has entered the state where the data signal is lost, a Data input signal, and an input deviation that the main memory or the RI10 device indicates the end of the read process. [Output signal for distinguishing access; 5T2-0 is a signal indicating the type of read processing and the halt state. Figure 1, 2nd ward. Heavy-17 Cow 3 Diagram lips 4 Diagram

Claims (1)

[Claims] In an information processing device including a central processing unit that performs virtual memory management, a conversion index buffer mechanism for converting a virtual address to a real address within the central processing unit;
a control circuit that supplies an input/output control signal, and when address translation is performed in the translation lookaside buffer mechanism, the real address specifies the contents of the main memory together with the real address corresponding to the virtual address from the virtual address. The control circuit generates a signal to distinguish between an address that specifies an external input/output device and an address that specifies an external input/output device, and the control circuit uses this signal to perform input/output operations corresponding to both main memory access and external input/output access. An information processing device characterized by being able to supply a control signal.