JPS6069745A - Data addressing system - Google Patents

Abstract

PURPOSE:To speed up the processing of a microcontroller for control by synthesizing a base address and an offset address consisting of a file attribute and a location address based upon it, through hardware, and producing an effective address. CONSTITUTION:A CPU A1 which knows previously which data area, which data, and in what order a CPU B3 accesses stores offset addresses consisting of file attributes and location addresses in a control information storage part 6 composed of FIF0 in access order. The CPU B2 when accessing data generates only a signal base address file invariably and specifies a data area group 40. Further, an address composition part 11 of hardware makes the offset address from CPU A1 and the base address from the CPU B2 into one to assist the selection of the data area.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF APPLICATION OF THE INVENTION The present invention relates to a microcontroller, and particularly to a data addressing method suitable for data access.

[Background of the invention]

Six high-level words (for example, POL) corresponding to the control system block diagram
: problem+u (Jriented Lan
Guafe).

The controlling microcontroller 2 executes the IT macro instruction corresponding to the arithmetic element of this block diagram.

On the other hand, the programmer kl, for example, C 几T (Catho
Simply connect the necessary valley operation element blocks (macro instructions) on the screen such as the control task (
Create a block diagram). At this time, the programmer needs each macro instruction to be in the 7th ζ of λjI, and the data access area (the programmer draws an abstract block with a line, and the 7th section of the block is not drawn at all). Create the original map one by one.

For this reason, in the past, (1) the structure of the accessor 0 data area was complicated due to the macro instruction's operation, and (2)
) However, the drawback is that the effective address tools for accessing the data area are complicated and the processing efficiency is reduced.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an address resolution system for achieving high-speed processing execution in a control microcontroller.

[Summary of the invention]

The execution unit of instructions left in the control microcontroller is executed in macroinstruction units corresponding to the control system block diagram. The processing structure of this macro instruction is divided into two types depending on the person.

(1) Data transfer and associated address calculation unit (11)
On the other hand, the ratio of @(1)aOl) to the actual arithmetic processing unit is usually determined by (1))lt).

Therefore, in order to speed up the execution process, use the address calculation section (1). It can be seen that improvement of the data 1 draining/regulating method can most efficiently achieve 1 speed.

[Embodiments of the invention]

The configuration and operation of an embodiment of the present invention will be described below. FIG. 1 shows the basic configuration of an elbow plate and a microcontroller 2 according to the present invention. In figure 2, l is a control system block;
2 is a processing unit CP'UB which executes macro commands;
Qut) This is the interface part using f. In other words, the CPU B2 receives the result (computation specification) that has been previously decoded by the CPU Al via the intern eighth section 3, and performs all computations accordingly.

At this time, the processing between CPUA and B is performed in parallel (pipeline system +111) by the interface section 3 using FIFO. Also, CPU from CPUAl
For example, the transfer of decoding milled rice to/from B5 can be carried out using DMA (
1) Direct MelnOryAccess) Performs the transfer. In this way, the CPUA (1) performs all advance decoding of the advanced language, and (il) instructs the CPUB to execute the command. In other words, the CPUA
For each macro instruction, UB can determine (a) which area's data should be requested, and (b) in what order. Therefore, CPUA can assist CPUB with addressing data. For this reason, the method shown in FIG. 2 was used as the data atranging method. This addressing method has the following characteristics.

(1) CPU B contains all areas referenced by macro instructions (l-1 generic name FILE (base address)
Specify only.

(2) CPU A follows the above base address <F
ILE attributes (A-N) and corresponding opening address (1-
t) and supports Φ offset address.

(3) Generate an effective address by combining the base address in (1) and the offset address in (2) using hardware.

Here, the reason for distinguishing between the offcent address kFILE attribute and the location address in (2) above is that (a) CpUA
(b) The actual data areas are distinguished by having different storage capacities.

FIG. 3 shows an effective address management functional block using the atranging method. In the figure, 4 is a data area referenced by CPUB, 5 is an extension unit that extends the base address issued by CPUB to an actual location address, and 6 is a CPU
A control information storage unit for the offset address filled in by A and g;
7 is an execution macro instruction currently being executed, and 8 is a group of preparation macro instructions to be executed next time onwards. Here, the control information storage section 6 is constituted by a FIFO, and is stored as many execution macro instructions as the number of times the data area 4 is accessed by the CPUA. Effective address calculation according to this addressing method is performed by the following CPUA and CPUB.

(1) The CPU B specifies access data only by FILE (base address), which is the generic name of the data area, without being aware of the type or point of the data area to be accessed.

(2) CPU A uses the address information (offcent address: pIL) of the data area that CPU B can access.
Ef! and individual address) are set in advance in the control information storage unit 6.

FIG. 4 shows a hardware support functional block for synthesizing the base address and offset address. Further, 9 is a decoder 9 which specifies the type (FA to F'N) to be accessed by FILE attribute Q (A to N) in the control information storage section 6. The effective address is obtained by outputting an offset address from the control information storage section 6 at the same time as the CPUB issues the base address, and combining the addresses. The offset address of the control information storage unit 60 is CP
Updated for each base address source line of UB.

Next, the data access method in CPUBI will be explained using Figure 5. In the figure, 11 is CPUB
12 is a decoder, 13 is C
In the program memory of PUB2, 40 is a data area group accessed by CPUB2, and 41 to 43 are individual data areas, which correspond to data area 4 in FIG.

(1) The CPU Al, which can know in advance which data of which data area the CPU B 2 will access in what order, assigns Fo and E attributes (A -N) and location address (1-A
) are stored in the access order.

(2) When accessing data, CPU 2 uses a single base address FILE.
+(i:g rows. However, at this point, CPUB2 has specified the data area group 40. Therefore, in order to access the data, first select the data area group 40 (41 to 43). ), it is imperative to select one data area.

(3) Therefore, in this system, the hardware-based address synthesis unit 11 is used to synthesize the offset address from CPUAl and the base address from CPLTB2 to support data area selection. In other words, the informal address management format is (a) as shown in Figure 2.
Base address; FILE, (1>) FiLE attribute, (
C) According to the three structures of individual addresses, it takes the ♂ salt form d. Therefore, as shown in FIG. 6, the data area can be selected based on the base address and the ILE attribute.

(4) Also, the actual leap address in the data area is εt4 by the offset address from CPUAl.
As shown in the figure, 'a' is buried.

In this way, the CPUB can access data by specifying a single address (I!11LE: base address) without being aware of the internal structure of the data area (the type and pointer of the data area to be accessed). In other words, by using this addressing method, (1) the effective address meter g'i for data access can be simplified, and (Ii) furthermore, all of the data area can be handled as an external register image. (ii) Therefore, it is possible to speed up the processing (7f).

Next, an example using this addressing method will be explained in detail.

First, using the FIFO in Figure 1 using Figure 7,
-The structure of the face portion 3 will be described.

31 is an instruction control unit for notifying the CPUB of execution instructions and other information; 32 is an input/output data unit for mutually notifying data for the CPUB to execute calculations and execution results of the calculations; 310 is an execution instruction unit for notifying the CPUB of instructions for macro instructions to be executed;
311uC1'UB input data section for providing data necessary for the operation of the macro instruction executed; 312 is C;
Output to notify CPUA of the result calculated by PUB.

The data section, or IO, is an internal special section for temporarily storing data in CPUB.

A CP using an interface section 3 having such components
A summary of the operation between UA-8 is shown below.

(1) Indication of macro instruction to be executed CPUB uses the execution instruction unit 31 to determine the macro instruction to be executed. For example, the CPU A (a) inputs only the first address of the macro instruction to be executed into the execution instruction unit 31 KCPUB, and (b) the CPU B inputs the internal (macro instruction to be executed) indicated by the execution instruction unit 31. (beginning of)
Transfer control to In other words, CPUB is simply the execution instruction unit 3.
Control can be transferred to the macro instruction to be executed by simply referring to the contents of 1. It is sufficient to simply perform processing equivalent to a so-called indirect command.

(2) Execution of macro instructions Execution of macro instructions always involves access processing of data necessary for the operation. In the example shown in FIG. 5, there are three types of data areas to be accessed: (a) input data section 311, (b) output data section 312, and (C) internal temporary storage section. The method for distinguishing between these areas is shown below.

(1) Area Distinction As mentioned above, area discrimination is performed by the control information storage unit 6 with the aid of offset addresses from the CPUA.

(11) Data access to each area with data input/output distinction (input/output)
output) is the read/write issued by CPUB.
This can be easily determined based on the e-signal.

Therefore, the CPUB can execute a macro instruction without being aware of which area's data is used to perform an operation and which area the result is output to.

In other words, the address held within the macro instruction is a single address.

Note that data transfer between the CPUA and the intern ace section 3 is performed using DMA transfer, although not shown. As a result, C1COUA can constantly monitor the status of the equipment to be controlled, or update input data from the monitor, without being aware of the operating status of CPUB.

〔Effect of the invention〕

According to the present invention, effective address calculation for data access can be simplified into one step as follows.

(1) All data areas are used in the external register image = 'J'.

(2) Addresses for data access can be unified.

[Brief explanation of the drawing]

Figure 1 shows the basic configuration of the microcontroller, Figure 2 shows the data addressing configuration, Figure 3 shows the effective address management system, and Figure 4 shows the node support board. Lock diagram, Figure 5 is an address synthesis block diagram, Figure 6 is a time chart of address synthesis, Figure 7 is a CPU
-B between c/) (This is a diagram of y surface boot 2. l... CPUA, 2... CPUB, 3... Inno surface group, 4... data area, 5... address extension 6... Control information storage unit, 9... Decoder, IO... Internal temporary storage unit, 31... Instruction control unit,
32... Input/output data section, 31O... Execution instruction section.

Claims (1)

[Claims] 1. A first processing device that prints a high-level language corresponding to the control system block diagram in advance, and obtains the decoding result from this first processing device to correspond to the calculation elements of the control system block diagram. a control microcontroller configured with a second processing device;
According to the macro instruction in the second processing device, the addresses of the access/data area are configured into two groups, upper addresses and lower addresses, and the second processing device manages only the upper addresses, and the 6g1 The data storage blowfish method is characterized in that the processing device performs U-filling on the lower address following the upper address filled in by the second processing device.