KR940003323B1 - Interface circuit between mbus and dsp module for multi-media data processing - Google Patents

Abstract

For the intelligent computer to process multi-media data, the interface circuit for the MBus and DSP module to support direct SRAM access of the DSP module comprises an SRAM interface (100) to access SRAM in the DSP module, a DPRAM interface (200) to access DPRAM in the DSP, a DSP96002 host interface (300) to access DSP96002 host interface, a latch unit (28) to control the control signal, an AND-gate (29) to change every MBus status signals into one, a DSP controller (30) for symbolization, an SRAM controller (31) and a DPRAM controller (32).

Description

Interface circuit of MBus and DSP module for multimedia data processing

1 is a simplified block diagram of a prototype computing unit (PCU) incorporating the inventive circuit.

2 is an operational algorithm flow diagram of an MBus interface circuit for SRAM, which is one of the circuits of the present invention.

3 is a program in which the algorithm of FIG. 2 is written in PDL.

4 is an SRAM interface circuit diagram and a simulation waveform diagram which is one of the circuits of the present invention.

5 is an operation algorithm flow diagram of the MBus interface circuit for DPRAM, which is one of the circuits of the present invention.

6 is a program in which the algorithm of FIG. 5 is written in PDL.

7 is a DPRAM interface circuit diagram and simulation waveform diagram which is one of the circuits of the present invention.

8 is a flowchart of an operation algorithm of the MBus interface circuit for the DSP96002 host interface of the present invention.

9 is a program in which the algorithm of FIG. 8 is written in PDL.

10 is an interface circuit and simulation waveform diagram for the DSP96002 host interface which is one of the circuits of the present invention.

11 is an overall flow chart of the present invention.

The present invention relates to an interface circuit between a digital signal processor (DSP) module and a node processor for processing multimedia data in an intelligent computer. In particular, the node processor is connected through a node processor SPAR and an MBus of a DSP module. The SRAM in the DSP module is directly accessible.

Prototype Computation Unit (PCU) of a conventional intelligent computer is a parallel processing unit in which two or three different processors form one node and perform tasks with nodes of the same structure as a whole. Must have arithmetic function

The first is to process knowledge information, the second is to process multimedia data, and finally to perform general purpose operations.

In order to process multimedia data among them, various functions such as fast processing and efficient processing of repetitive loops are required. Therefore, a DSP chip dedicated to multimedia data processing is used separately from a node processor.

An object of the present invention is to provide an interface circuit of an MBus and a DSP module so that a DSP for processing multimedia data is connected through a node processor SPAR and an MBus, and the node processor can directly access an SRAM in a DSP module through an MBus interface.

The present invention made to achieve the above object is a node constituting the PCU is a node processor (1) SPARC, node memory (2), the inter-node communication (IN) (5) that manages communication between nodes, and auxiliary memory (Secondary storage) (2) consists of a channel to access, a DSP module (3) to process multimedia data, and VMEIF (VMEIF) (4) to provide a connection with the host computer when these nodes act as a back end. do.

The DSP module has a DSP96002 processor that processes multimedia data and a large amount of time loss when the DSP processor accesses data from node memory to process a large amount of multimedia data. SRAM for processing multimedia data and DPRAM (Dual Port SRAM) for communication with SPARC, a node processor, these elements have an MBus interface.

The MBus interface consists of a part for the DSP96002 processor, a part that allows the node processor to directly access the SRAM in the DSP module, and a part that allows the node processor to access the DPRAM.

Details of each part are as follows.

1) SRAM Interface

This section describes the generation of signals for SRAM control of the DSP module using Mbus control signals as inputs.

SRAM control signals are as follows.

S_CS ^* : SRAM chip select signal.

S_WE ^* : SRAM Write Enable signal.

S_OE ^* : SRAM Output Enable signal.

In Fig. 2, the algorithm used to generate the above three signals is simplified.

In Figure 2, the SRAM interface portion consists of three levels and operates in four states.

In Idle state 7, the interface part waits for the SRAM_CS signal to be input from the decode.

When the SRAM_CS signal is input, the Local Bus Request signal LBR * (Local Bus Request) signal is output to the Local Bus Arbiter, and MBB ^* , MBG ^* signals are output before the state transition to the next state (8). With the value "Low", and if the MAS signal is an address cycle (ie MAS ^* = '0'), set the latch operation signal LCE to latch the address.

In the next state (8), the MCE resets LCE after one clock cycle.

In the next state (8), it waits for the use of the local bus intermediate machine.

If Local Bus Grant (LBG *), Local Bus Grant, has a value of “Low” and Mbus is a data cycle (ie MAS ^* = '1'), set S_CS, S_OE, and set the LOE (Letch Output Enable) signal. To the local address bus that was latched.

Finally, the read and write of the memory is determined by the MAD [36] signal, which moves (9, 10) to the read and write states, and the MAD [35: 0] and the local data bus ( Transfer output signal TOE ^* for connecting Local Data Bus) and TDR ^* signals for determining the direction of connection have their own values.

In any state, when RESET signal is input, it initializes all output values and moves to Idle state (7).

If an error occurs in the Mbus, the control returns MERR ^* , BRDY ^* . BTRY ^* Three signals inform the node processor of the state of the Mbus and then move to Idle state (7).

The above algorithm is written as a program (Figure 3) using PDL (PLDSynthsis Design Language) and then compiled using the pld compiler.

The compilation results in a Jedec file for the two PALs (Programmable Array Logic).

The circuit was designed using two PALs (11, 12), and then the Jedec file for each PAL was input to the PAL to complete the SRAM interface circuit for MBus.

4 shows an SRAM interface circuit and an operating waveform diagram.

The waveform diagram 13 shows the complete cycle for the node processor to write access to the SRAM.

2) DPRAM Interface

This section describes the generation of the following DPRAM control signals using Mbus control signals.

DP_CS ^* : DPRAM Chip Select signal.

DP_WE ^* : DPRAM Write Enable signal.

DP_OE ^* : Output enable signal.

5 simply illustrates the algorithm required to generate the above three signals.

Wait for the DPRAM_CS ^* signal to be active in Idle state 14.

After synchronization, the MBB ^* and MBG ^* signals are checked, the MAS ^* signal is checked for an address cycle (i.e., MAS ^* = 0), and if all conditions are satisfied, the latch operation signal LCE is set to latch the address. If MAS ^* = 1, Mbus is a data cycle, so the LOE ^* signal is set to input the latched address into DPRAM, the TOE ^* signal is set to move data between DPRAM and Mbus, and the TDR signal determines the data transfer direction. Determine the value.

The above operation is similar to the SRAM interface part, or if the node processor accesses DPRAM, it does not use the local bus of the DSP module, so it does not need to be controlled by the local bus arbiter. Move from Idle state to Read / write state (16, 17) without waiting for signal.

The three signals MERR ^* , BRDY ^* , MTRY ^* generate the corresponding error as in the SRAM interface and inform the node processor via Mbus.

5, the algorithm also uses PLD to write a program (Fig. 6), and compiles the DPRAM interface circuit (Fig. 7) with two PALs 18 and 19 through compilation and the like.

The waveform diagram 20 shows one cycle in which the node processor writes access to the DPRAM.

3) DSP96002 Interface

This section inputs MBus control signals to generate signals that control the DSP_HI (Host Interface), allowing the node processor to directly access the internal registers or internal memory of the DSP96002 processor.

DSP_HI control signals are as follows.

R / W ^* : Read / write selection signal.

HS ^* : Host Sclect signal.

HA ^* : Host Acknowledge signal.

TS ^* : Transfer Stroe signal.

HR ^* : Host Request signal.

8 simply illustrates an algorithm for generating the above control signals.

In FIG. 8, if the DSP_cs signal is set in Idle state 21, and the MBB ^* and MBG ^* signals have a value of “Low”, the interface makes a local bus request to use the local bus (LBR ^* <= 0). , Mbus sets the latch operation signal (LE ^* <= 0) to latch the MDA [2] -MAD [5] value with information about the DSP_HI function during the address cycle (MAS ^* = 0).

In the next situation, the local bus master waits for a local bus license.

When the enable signal (LBG * = 0) is input, the latched address is loaded on the local bus (LOE ^* <= 0), allowing the TS ^* , HS ^* , and HA ^* signals to have unique values.

Next, read and write (23, 24) status is determined by MAD [36] value. If Mbus is data cycle (MAS ^* = 1), connect MbusMAD [31: 0] and Local Data [31: 0]. (TOE = 1), the data transfer direction, i.e., the TDR ^* signal, has the value according to the MAD [36] value.

The MRDY ^* value is set to "Low" to inform the node processor of the arrival of the data.

FIG. 10 is an interface circuit created with the two PALs 25 and 26 through the pld compilation and the like, which is also written in the PDL program (Figure 9).

Figure 11 shows the MBus interface circuit for the DSP module using the three interface circuits above.

Each interface circuit is designed with a single symbol (30, 31, 32), and MBus is a single type bus that uses a hydrogen bus and a data bus together. (MAD [36, 40, 41]) uses latch 28 to latch its value and then use it when MBus is a data cycle.

When the node processor accesses the DSP96002 processor and the SRAM, it uses the local bus, so that the signals controlling the connection to the MBus are generated at the DSP interface and the SRAM interface, respectively, and a single signal to the AND gate or the OR gate 35. Made with.

And when operating in the three interface circuits MERR is generated to indicate the status of the MBus ^*, MROY ^*, the MRTY ^* signal also to the AND gate 29 made into one signal.

The INT (Interrupt) signal is designed to be available when the interrupt value for the DSP module is given in the overall node design. In FIG. 11, the interrupt signal is limited to the DSP96002 processor used when requesting the node processor.

As described above, according to the present invention, the DSP module for processing multimedia data is connected through the node processor SPAR and MBus, and the node processor has an effect of enabling direct access to the SRAM in the DSP module through the MBus interface.

Claims (2)

An intelligent computer for processing multimedia data, comprising: SRAM interface means (100) for accessing SRAM in a DSP module, DPRAM interface means (200) for accessing DPRAM in a DSP module, and DSP96002 hose interface in a DSP module. The interface circuit of the MBus and DSP module for multimedia data processing, characterized in that for direct access to the SRAM in the DSP module by the DSP96002 host interface means (300) for accessing. The method of claim 1, wherein the SRAM interface, the DPRAM interface, and the interface of the DSP96002 are used to configure the MBus interface means 400 of the node processor (SPARC) for the DSP96002 processor, and the SRAM interface means for accessing the SRAM ( 100 is a DPRAM interface means for accessing the DPRAM with two PALs 11 and 12, and a DSP96002 host for accessing the DSP96002 host interface with two PALs 18 and 19. The interface means 300 is composed of two PALs 25 and 26, and the MBus interface means 400 of the node processor for the DS96002 processor includes a latch unit 28 for latching a control signal MAD value. And an AND gate 29 for generating MERR, LMRDY, and MRTY signals generated to indicate the status of the MBus into a single signal, a DSP controller 30 for symbolizing, an SRAM controller 31, and a DPRAM 32. And, Andgate ( 33), (34), and the interface circuit of the MBus and DSP module for multimedia data processing, characterized in that it consists of an end gate or an or gate (35) to produce a signal to control the connection to the MBus as a single signal.