JPS60233933A - プログラム可能な論理アレイ - Google Patents

プログラム可能な論理アレイ

Info

Publication number
JPS60233933A
JPS60233933A JP59089685A JP8968584A JPS60233933A JP S60233933 A JPS60233933 A JP S60233933A JP 59089685 A JP59089685 A JP 59089685A JP 8968584 A JP8968584 A JP 8968584A JP S60233933 A JPS60233933 A JP S60233933A
Authority
JP
Japan
Prior art keywords
logic
logical
time
pla
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59089685A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0578972B2 (enExample
Inventor
Tadahide Takada
高田　正日出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59089685A priority Critical patent/JPS60233933A/ja
Publication of JPS60233933A publication Critical patent/JPS60233933A/ja
Publication of JPH0578972B2 publication Critical patent/JPH0578972B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
JP59089685A 1984-05-04 1984-05-04 プログラム可能な論理アレイ Granted JPS60233933A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59089685A JPS60233933A (ja) 1984-05-04 1984-05-04 プログラム可能な論理アレイ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59089685A JPS60233933A (ja) 1984-05-04 1984-05-04 プログラム可能な論理アレイ

Publications (2)

Publication Number Publication Date
JPS60233933A true JPS60233933A (ja) 1985-11-20
JPH0578972B2 JPH0578972B2 (enExample) 1993-10-29

Family

ID=13977620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59089685A Granted JPS60233933A (ja) 1984-05-04 1984-05-04 プログラム可能な論理アレイ

Country Status (1)

Country Link
JP (1) JPS60233933A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154315A (ja) * 1984-12-21 1986-07-14 ナームローゼ　フエンノートチヤツプ　フイリツプス　グロエイラムペンフアブリーケン 無比率ｆｅｔプログラム可能論理配列
JPS6333923A (ja) * 1986-07-23 1988-02-13 エイ・ティ・アンド・ティ・コーポレーション Ｃｍｏｓプログラマブル論理配列
JPS6397014A (ja) * 1986-10-14 1988-04-27 Matsushita Electric Ind Co Ltd プログラマブルロジツクアレイ
JPS63177615A (ja) * 1987-01-19 1988-07-21 Oki Electric Ind Co Ltd 半導体論理回路
JPH01175414A (ja) * 1987-12-29 1989-07-11 Fujitsu Ltd 半導体集積回路
JPH03231515A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp プログラマブル論理装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154315A (ja) * 1984-12-21 1986-07-14 ナームローゼ　フエンノートチヤツプ　フイリツプス　グロエイラムペンフアブリーケン 無比率ｆｅｔプログラム可能論理配列
JPS6333923A (ja) * 1986-07-23 1988-02-13 エイ・ティ・アンド・ティ・コーポレーション Ｃｍｏｓプログラマブル論理配列
JPS6397014A (ja) * 1986-10-14 1988-04-27 Matsushita Electric Ind Co Ltd プログラマブルロジツクアレイ
JPS63177615A (ja) * 1987-01-19 1988-07-21 Oki Electric Ind Co Ltd 半導体論理回路
JPH01175414A (ja) * 1987-12-29 1989-07-11 Fujitsu Ltd 半導体集積回路
JPH03231515A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp プログラマブル論理装置

Also Published As

Publication number Publication date
JPH0578972B2 (enExample) 1993-10-29

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