JPS6022855A - ビツト同期クロツク発生装置 - Google Patents

ビツト同期クロツク発生装置

Info

Publication number
JPS6022855A
JPS6022855A JP59132556A JP13255684A JPS6022855A JP S6022855 A JPS6022855 A JP S6022855A JP 59132556 A JP59132556 A JP 59132556A JP 13255684 A JP13255684 A JP 13255684A JP S6022855 A JPS6022855 A JP S6022855A
Authority
JP
Japan
Prior art keywords
signal
frequency
counter
clock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59132556A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0123979B2 (enrdf_load_stackoverflow
Inventor
Kiyoshi Kawana
川名　清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59132556A priority Critical patent/JPS6022855A/ja
Publication of JPS6022855A publication Critical patent/JPS6022855A/ja
Publication of JPH0123979B2 publication Critical patent/JPH0123979B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
JP59132556A 1984-06-27 1984-06-27 ビツト同期クロツク発生装置 Granted JPS6022855A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59132556A JPS6022855A (ja) 1984-06-27 1984-06-27 ビツト同期クロツク発生装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59132556A JPS6022855A (ja) 1984-06-27 1984-06-27 ビツト同期クロツク発生装置

Publications (2)

Publication Number Publication Date
JPS6022855A true JPS6022855A (ja) 1985-02-05
JPH0123979B2 JPH0123979B2 (enrdf_load_stackoverflow) 1989-05-09

Family

ID=15084046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59132556A Granted JPS6022855A (ja) 1984-06-27 1984-06-27 ビツト同期クロツク発生装置

Country Status (1)

Country Link
JP (1) JPS6022855A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5222868A (en) * 1975-08-14 1977-02-21 Kokusai Denshin Denwa Co Ltd <Kdd> Fs demodulator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5222868A (en) * 1975-08-14 1977-02-21 Kokusai Denshin Denwa Co Ltd <Kdd> Fs demodulator

Also Published As

Publication number Publication date
JPH0123979B2 (enrdf_load_stackoverflow) 1989-05-09

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