JPS6020952B2 - Synchronous separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a sync separation circuit that separates a sync signal from a vedestally clamped TV signal.

Generally, input TV signals have frequency fluctuations, so in order to separate the synchronization signal from the TV signal, it is necessary to operate over a wide input dynamic range of the TV signal. For this reason, the synchronization signal is detected by an auto bias circuit. This will be explained using the conventional example shown in FIG. In the figure, 1 is an inverting amplifier, 2 is a capacitor, 3 is a transistor, 4 is a waveform shaping circuit, 5 is a resistor, and V8 is a voltage source. The TV signal inputted in FIG.

In this case, the synchronizing signal of the TV signal is charged in the capacitor 2. Here, the charging voltage Vc of the capacitor 2 and the simplified emitter base voltage V of the transistor 3 are assumed to be. When the synchronization signal level exceeds Vc10V as shown in Fig. 2a in the detection circuit using an auto-bias circuit consisting of a resistor 5, a capacitor 2, and a transistor 3, the transistor 3 turns on and a synchronization separation circuit is constructed. . Here, D is called vedestal. The output of the synchronously separated transistor 3 is shaped into a synchronous signal by a waveform shaping circuit 4. In this case, when the transistor 3 is turned ON and OFF by the synchronization signal, the fall of the synchronization signal A (pulse width t,) shown in FIG. This results in a synchronizing signal (pulse width t2) such as C, and the pulse width is expanded by t=t2-t, which is not suitable for creating the clock pulses necessary for encoding.

The auto-bias synchronizing signal detection circuit described above as a subsidiary example has the following drawbacks. 1. It is difficult to adjust the bias setting of transistor 3 and the dynamic range due to input level fluctuations.

2. It is difficult to generate a faithful synchronization signal (accurate synchronization pulse width).

This makes it difficult to generate clock pulses from the synchronization signal and perform image processing, which is the purpose of the synchronization separation circuit.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a circuit that detects a stable synchronization signal with respect to level fluctuations of the W signal.

To this end, the objective is to improve the items described above.

1. Faithful reproduction of synchronization pulse width.

2 Simplification of adjustment method.

3. Realization of a synchronous separation circuit that is resistant to noise.

For the above purpose, the following embodiment will be explained with reference to FIG.

In the figure, 6 is an input terminal, 7 is a synchronization pulse output terminal, 8 is an operational amplifier, and 9 is a first operational amplifier (hereinafter referred to as operational amplifier 9).
10 is a second operational amplifier (hereinafter referred to as operational amplifier 1), 10 is a second operational amplifier (hereinafter referred to as operational amplifier 1
0), 11 is a synchronous pulse detection circuit (hereinafter referred to as detection circuit 11), and 12 is a peak detection circuit (capacitor 1).
3, a diode 14, and a resistor 24.

) 15 is the output voltage Vo of the operational amplifier 8, 16 is the reference voltage 1, 17 is the operating voltage Vd of the diode 14, 18 is the reference voltage D, 20 is the resistor R2, 21 is the resistor R5, 25 is the resistor father 3, 26 is the Resistors R4, 19, 22, 23, and 24 represent resistances. In FIG. 3, the phase of the Vedestal-clamped TV signal input to the input terminal 6 is inverted by the operational amplifier 8, and input to the peak detection circuit 12 and the detection circuit 11.

The peak detection circuit 12 performs peak rectification in which the synchronous pulse signal portion of the TV signal is set as a peak value. The output of the peak detection circuit 12, which is proportional to the peak value of the synchronization pulse, is input to the operational amplifier 9, compared with the reference voltage 1 (Vs,) 16, amplified, and returned to the operational amplifier 8. With the above configuration, the peak voltage change of the output signal of the operational amplifier 8 is amplified by the operational amplifier 9 and fed back as a larger change, so the output voltage of the peak detection circuit 12 is set to the reference voltage 1 (Vs,
)16, and as a result, the output signal of the operational amplifier also has an output voltage ((
Vo) 15 is obtained.

On the other hand, the output signal of the operational amplifier 9 is also input to the operational amplifier 10, compared with a reference voltage (Vs2) 18, amplified, and input to the detection circuit 11.

In this case, the bias conditions of the calculation environment Taifu device 10 and its peripheral circuits are set as follows.

Cod Foot = Kyou/Masu Kai…….

'Ship)・8; Seiki side・7 10 (Vs,) 16} ...... [2'.

(R5)《{・Juzoroki}・(R2)2o...A31 From the above conditions, the output voltage of the operational amplifier 10 is the TV signal controlled by the loop of operational amplifier 8 - peak detection circuit 12 - operational amplifier 9. (Vo) 15 synchronization pulse peak value V
Voltage between OP and bedestal level Vpd = Season (V
. p10Vpd). This voltage is input to the detection circuit 11, and the TV signal (V
o) Detect synchronization pulse by sampling 15. This state will be described in FIGS. 40a, b, and c. Figure a shows a TV signal, and Figure b shows a signal obtained by inverting the TV signal, with the waveform of (Vo) 15, 27 the peak value Vop of the synchronizing pulse, 28 the threshold voltage Vp, and 29 the final level Vpd.

Figure c shows the synchronization pulse output from the detection circuit 11.

To summarize the above, the output voltage 0 voltage (Vo) 15 of the operational amplifier 9 whose threshold level and peak voltage are controlled to be constant is input to the detection circuit 11 that outputs the synchronization pulse, and the voltage at the middle of the synchronization pulse is input. Since the synchronization pulse is detected using the above signal, the detection circuit 11 outputs a stable synchronization pulse.

Next, the features of the present invention will be described. '1} Adjustment is easy.

In other words, the adjustment points are the synchronous separator, the reference voltage 1 (Vs,) 16 that determines the possible dynamic range, and the reference voltage 0 (Vs2) that determines the threshold level of the detection circuit 11.
There are 2 locations, 18, and adjustment is easy. (It is also possible to set the value to a fixed value in advance.) ■ Since the threshold level Vth of the detection circuit is set at an intermediate position of the synchronization pulse, the synchronization pulse can be reproduced faithfully.

'31 When not only low frequency noise but also high frequency noise is superimposed on the TV signal, the TV signal (Vo) 15 of the operational amplifier is
Even if it is not possible to compress the peak value (Vop) 27 of This makes the circuit extremely resistant to high frequency noise.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional example, Figures 2a and b are waveforms of synchronizing pulses of a TV signal to explain Figure 1, Figure 3 is an embodiment of the present invention, Figures 4a, b, c shows the TV signal, Vo waveform, and synchronization pulse for explaining FIG. In the figure, 1 is an inverting amplifier, 2 and 13 are capacitors, 3 is a transistor, 4 is a waveform shaping circuit, 5 is a resistor, 8, 9, 1
0 is an operational amplifier, 11 is a detection circuit, 12 is a peak detection circuit, 14 is a diode, 15 is Vo, 16 is Vs, 1
8 represents Vs2, 20 represents resistor R2, 21 represents resistor R5, 25 represents R3, and 26 represents R4. Figure 1 Figure 2! Sail Figure 2 rb) Figure 3 Figure 4

Claims (1)

[Claims] 1 An operational amplifier that increases the pedestal-clamped TV signal to a predetermined level, and a peak detection circuit that performs peak detection on one of the branched outputs of the operational amplifier and outputs a peak detection voltage proportional to the synchronization pulse of the TV signal. a first operational amplifier inputting the peak detection voltage and a first reference voltage and feeding back one of its outputs to the input of the operational amplifier; the other branching the output of the first operational amplifier; a second operational amplifier having means for inputting a reference voltage and shaping a threshold value of the synchronization pulse which is an intermediate voltage between the peak value of the synchronization pulse and the pedestal level; A synchronization separation circuit characterized in that the synchronization pulse is detected from the other branched output of the input operational amplifier.