JPH0527737A - Synchronization separating circuit - Google Patents

Abstract

PURPOSE:To obtain such excellent characteristics that the phase of a picture on a CRT screen becomes stable by the synchronous separating circuit which separates a synchronizing signal from a composite video signal generated by superposing the video signal and synchronizing signal of a CRT display device upon the output signal of a computer. CONSTITUTION:The circuit consisting of inverting and amplifying circuits Q1 and Q2, and R3 and R4 which invert and amplify a signal through an input coupling capacitor circuit C1, an amplifying circuit which amplifies and outputs a signal with a constant threshold level with the inverted and amplified signal, rectifying circuits D1 and C2, and Re which perform the peak amplification of the inverted and amplified signal, level comparing and amplifying circuits Q4 and Q5, and R7-R10 which perform the level comparison and amplification of the peak-rectified signal, and an impedance circuit R1 which applies the output signals of the level comparing and amplifying circuits to the inputs of the inverting and amplifying circuits makes the DC voltage value of the peak of the synchronizing signal of the output signal of the inverting and amplifying circuit invariably constant not to vary the synchronism-separated output signal in phase and pulse width with the contents of the video.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display device for displaying an output signal from a computer and to a sync separation circuit for separating a sync signal from a composite video signal in which a video signal and a sync signal are superimposed.

[0002]

2. Description of the Related Art In recent years, a computer has been required to have a high display density due to an increase in memory capacity and an increase in processing speed. As a result, the display device CR
A T display device having a dramatically high synchronization / deflection frequency is required, and a sync separation circuit with good performance is required.

A conventional synchronization separation will be described with reference to the drawings.
The circuit will be described. FIG. 4 shows an example of a conventional sync separation circuit.
It shows an example. In FIG. 4, C₁₁Is the input coupling
Indexer, R₁₁And R₁₂Is the base bias resistance, Q₁₁Is
Ramp with grounded emitter₁₃And R₁₄Each
Q₁₃Emitter resistance and collector resistance, Q ₁₂Is the emitter
Lower transistor, R₁₅Is Q₁₂Emitter resistance of I
C₁₁Is an invar with a certain threshold level
This is where the actual sync separation takes place.

The circuit operation of FIG. 4 will be described. A composite video signal having a positive video signal and a negative sync signal as shown in FIG. 5A is applied to the input terminal (a).

Generally, this composite video signal is 1.0 V _pp.
Since the amplitude is too small for synchronous separation as it is, it is amplified by the amplifier circuit Q ₁₁ and amplified as shown in FIG. 5B and added to the next synchronous separation stage.

A signal as shown in FIG. 5 (C) is added to the input of the synchronous separation stage IC ₁₁ , and the threshold level V of IC ₁₁ is added.
_{The th} signal portion is amplified, and only the synchronizing signal is separated and output to the output (d) as shown in FIG. 5 (d).

The deflection circuit operates based on this synchronization signal.

[0008]

The problem here is that the phase and pulse width of the separated sync signal change depending on the contents of the video signal, which changes the phase of the video on the CRT screen. .. The situation will be described in detail below.

Signals at points (C) and (d) in the circuit diagram of FIG. 4 will be described. Generally, in the composite video signal, as shown in FIG. 6A, the pulse portion of the synchronization portion has a rising and falling slope. Therefore, if the sync separation threshold level changes, the sync separation output signal also changes. Now, assuming that the threshold level is changed from V _th1 to V _th2 in the signal waveform shown in FIG. _6A , the sync separation output has the phase and pulse of the sync signal pulse as shown in FIGS. 6B and 6C, respectively. The width varies. Generally, when the phase of the sync pulse changes, the phase of the screen also changes.

If the horizontal phase of the sync signal advances, the horizontal phase of the image lags relatively, and the image on the CRT screen moves to the right.

The fluctuation of the threshold level actually occurs in the following cases. This will be described with reference to FIG.

FIG. 7 shows the signal waveform at point (C) in the circuit of FIG. The operation of the circuit of FIG. 4 is such that the input is a capacitor coupling, and operates based on the average value level of the signal. Therefore, when there are many white signals in the content of the video signal, the average level V ₀ of the signal is near the center of the video signal as shown in FIG. 7A, and the signal waveform appearing at point (C) is the sync signal. The signal waveform is such that the tip reaches a high voltage value.

On the other hand, in the case of a signal having many black signals, the average level V _{0 of the} signal is near the black level of the image portion,
The signal appearing at point (C) has a signal waveform with a low voltage value at the synchronous peak as shown in FIG. 7 (b). As a result,
In the case of (a), the sync signal is separated near the center of the sync signal, and in the case of FIG. 7 (b), the sync signal is separated near the leading end of the sync signal. Images with a lot of white signals (Fig. 7B).
When it changes to (a)), the phase of the sync separation output advances and CR
The image on the T screen moves to the right.

The structure as shown in FIG. 4 has a problem that the phase of the video signal on the CRT screen moves depending on the contents of the video signal as described above.

In view of the above problems, it is an object of the present invention to provide a sync separation circuit for a CRT display, which performs a stable operation without the phase of the video signal on the CRT screen shifting due to the contents of the video signal.

[0016]

In order to achieve this object, a sync separation circuit of the present invention comprises an inverting amplifier circuit for inverting and amplifying a signal via an input coupling capacitor circuit, and a constant threshold value for the inverted and amplified signal. In a sync separation circuit including an amplifier circuit for amplifying a level signal and outputting the signal, the inverted / amplified signal is subjected to peak rectification, the peak rectified signal is added to a level comparison / amplification circuit, and the level comparison / amplification circuit is provided. The output signal of 1 is applied to the input of the inverting amplifier circuit via an impedance circuit.

[0017]

With this configuration, the peak level of the sync signal of the amplified composite video signal, which is the input signal of the sync separation stage, is always kept constant, and the threshold level for sync separation is always constant from the leading end value of the sync portion. This is performed so that the phase and pulse width of the synchronously separated output signal do not change depending on the contents of the image, and the phase of the image on the CRT screen does not move.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sync separation circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit of an embodiment of the present invention. C
₁ is an input coupling capacitor, Q ₁ and Q ₂ are Darlington-connected transistors, which together with an emitter resistor R ₃ and a collector resistor R ₄ constitute a grounded-emitter inverting / amplifying circuit, and R ₂ is between the base and emitter of Q _2. Is a resistor connected to.

Q ₃ is a transistor which constitutes an emitter follower circuit together with the emitter resistor R ₅ , IC ₁ is an integrated circuit of an inverter circuit, D ₁ is a diode which constitutes a peak rectifying circuit together with a capacitor C ₂ and a resistor R ₆ , Q ₄ , Q ₅ is a level comparison circuit which constitutes a differential amplifier circuit together with the emitter resistance R ₇ , the collector resistance R ₈ and the base bias resistances R ₉ and R ₁₀ .

R ₁ is a resistor which serves as an impedance circuit for negatively feeding back the signal from the output of the level comparison circuit to the input stage.

The operation of FIG. 1 will be described. The basic operation from points (a) to (C) is the same as that of the conventional example shown in FIG. 4, except that a Darlington circuit having a high input impedance is used in the input stage.

The characteristic operation from point (C) to point (e) will be described. The signal at point (C) is changed to D ₁ , C ₂ ,
The signal at point (d) rectified by the peak rectifying circuit of R ₆ is input to the level comparing circuit of Q ₄ and Q ₅ and compared with the voltage value determined by the bias circuit of R ₉ and R ₁₀ , and if (d) When the voltage at the point is lower than the voltage at the point (e), the current flowing through Q ₅ is small and the voltage across the terminals of R ₈ is small, so that the input DC voltage of the amplification inverting circuit is Q ₁ via the resistor R _{1 of the} impedance circuit. , Q _{2 is controlled so that} the base voltage of Q ₂ is lowered, and as a result, the output DC voltage level at the point (b), which is the output of the amplification and inverting output circuit, is controlled to be higher, so that the DC voltage level at the point (C) becomes higher ( The DC voltage at point (d) obtained by rectifying the peak value at point C) is controlled to be high.

On the other hand, if the voltage value at the point (d) is higher than the voltage value at the point (e), the operation reverse to the above operation is performed to lower the DC voltage level at the point (d). In this way, the circuit operates so that the voltage at point (d) is always equal to the voltage at point (e).

Controlling that the DC voltage level at point (d) is always a constant voltage means that the peak voltage value of the sync signal of the composite video signal appearing at point (C) is always constant. Will be controlled.

If the peak voltage value of the sync signal of the composite video signal appearing at the point (C) is controlled to be always constant, the content of the video signal of the signal at the point (C) is shown in FIG. As shown in FIG. 2, in the case of a composite video signal having many white signal components, even if the average DC level of the signal is near the middle of the video signal,
In the case of a composite video signal having many black signal components in the video signal as shown in (b), the signal at point (C) is the peak voltage of the sync signal even if the average DC level of the signal is near the black signal of the video signal. The value always appears to be controlled to be equal to the voltage at point (e) plus the forward voltage of diode D ₁ .

Since the operation as described above means that the DC level of the signal is always constant, the threshold level voltage V for synchronous separation is set.
_Since the portion facing _th is constant regardless of the contents of the video signal, the phase and pulse width of the sync separation output signal are always constant.

As a result, it is possible to display a stable image without the inconvenience that the phase of the image signal on the CRT screen shifts depending on the contents of the image signal as in the conventional example.

In FIG. 1, an inverter circuit is used in IC ₁ to generate a negative sync signal for the sync separation output signal. However, if it is desired to obtain a positive sync separation output, FIG.
As shown in (a) and (b), a signal can be obtained by using a gate circuit having an AND circuit or an OR circuit configuration.

[0030]

INDUSTRIAL APPLICABILITY As described above, the present invention is an inverting amplifier circuit that inverts and amplifies a signal via an input coupling capacitor circuit, and an amplifier circuit that amplifies a signal obtained by inverting and amplifying a constant threshold level signal and outputs the signal. By providing a rectifier circuit for rectifying the inverted / amplified signal to a peak, a level comparison / amplifier circuit, and an impedance circuit, the peak level of the sync signal of the amplified composite video signal, which is the input signal of the sync separation stage, is always maintained. Keep the threshold constant, and make sure that the threshold level for sync separation is always more constant than the leading edge of the sync part so that the phase and pulse width of the sync separated output signal does not change depending on the contents of the video, and the CRT screen It is possible to realize excellent characteristics that can prevent the phase of the above image from moving.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a sync separation circuit of the present invention.

FIG. 2 is a waveform diagram for explaining the operation in the same embodiment.

FIG. 3 is a partial circuit diagram of another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional sync separation circuit.

FIG. 5 is a waveform diagram for explaining the operation of the conventional example.

FIG. 6 is a waveform chart for explaining the operation of the conventional example.

FIG. 7 is a waveform diagram for explaining the operation of the conventional example.

[Explanation of symbols]

C ₁ , C ₁₁ Input coupling capacitors Q ₁ , Q ₂ Darlington connected emitter-grounded amplification transistor R ₁ Impedance resistor R ₂ Q ₂ Resistors connected between base and emitter R ₃ , R ₅ , R ₇ , R ₁₃ , R ₁₅ Emitter resistance R ₄ , R ₈ , R ₁₄ Collector resistance Q ₃ , Q ₁₂ Emitter follower circuit transistor IC ₁ , IC ₁₁ Inverter circuit integrated circuit D ₁ Rectifier diode R ₆ Rectifier circuit discharge Resistor C ₂ Rectifying capacitor Q ₄ , Q ₅ Transistors connected to differential amplifier circuit R ₉ , R ₁₀ , R ₁₁ , R ₁₂ Base bias resistor Q ₁₁ Common emitter type amplification transistor

Claims (1)

Claim: What is claimed is: 1. An inverting amplifier circuit that inverts and amplifies an input composite video signal via a coupling capacitor circuit, and an amplifier that amplifies and outputs a signal having a constant threshold level of the inverted and amplified signal. A circuit for peak rectifying the inverted / amplified signal and comparing the level of the peak rectified signal.
In addition to the amplification circuit, a sync separation circuit in which the output signal of the level comparison / amplification circuit is applied to the input of the inverting amplification circuit via an impedance circuit.