JPS60204118A - 任意の論理関数を実現する方法及び装置 - Google Patents

任意の論理関数を実現する方法及び装置

Info

Publication number
JPS60204118A
JPS60204118A JP59059882A JP5988284A JPS60204118A JP S60204118 A JPS60204118 A JP S60204118A JP 59059882 A JP59059882 A JP 59059882A JP 5988284 A JP5988284 A JP 5988284A JP S60204118 A JPS60204118 A JP S60204118A
Authority
JP
Japan
Prior art keywords
line
signal
storage means
product term
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59059882A
Other languages
English (en)
Japanese (ja)
Inventor
Masahiko Washimi
鷲見　昌彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59059882A priority Critical patent/JPS60204118A/ja
Priority to US06/716,388 priority patent/US4710898A/en
Priority to DE19853511375 priority patent/DE3511375A1/de
Priority to DE3546596A priority patent/DE3546596C2/de
Publication of JPS60204118A publication Critical patent/JPS60204118A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP59059882A 1984-03-28 1984-03-28 任意の論理関数を実現する方法及び装置 Pending JPS60204118A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59059882A JPS60204118A (ja) 1984-03-28 1984-03-28 任意の論理関数を実現する方法及び装置
US06/716,388 US4710898A (en) 1984-03-28 1985-03-27 Apparatus for performing desired logical function
DE19853511375 DE3511375A1 (de) 1984-03-28 1985-03-28 Vorrichtung zur durchfuehrung gewuenschter logischer funktionen
DE3546596A DE3546596C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1984-03-28 1985-03-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59059882A JPS60204118A (ja) 1984-03-28 1984-03-28 任意の論理関数を実現する方法及び装置

Publications (1)

Publication Number Publication Date
JPS60204118A true JPS60204118A (ja) 1985-10-15

Family

ID=13125953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59059882A Pending JPS60204118A (ja) 1984-03-28 1984-03-28 任意の論理関数を実現する方法及び装置

Country Status (3)

Country Link
US (1) US4710898A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS60204118A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (2) DE3511375A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374321A (ja) * 1986-09-18 1988-04-04 Toshiba Corp 書込み可能な論理集積回路
WO1999042928A1 (en) * 1998-02-20 1999-08-26 Sowa Institute Of Technology Co., Ltd. Method of learning binary system

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5062080A (en) * 1987-08-03 1991-10-29 Motorola, Inc. Method and apparatus for enabling a memory
US4930098A (en) * 1988-12-30 1990-05-29 Intel Corporation Shift register programming for a programmable logic device
US5144582A (en) * 1990-03-30 1992-09-01 Sgs-Thomson Microelectronics, Inc. Sram based cell for programmable logic devices
EP0613249A1 (en) * 1993-02-12 1994-08-31 Altera Corporation Custom look-up table with reduced number of architecture bits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1219259B (de) * 1965-03-05 1966-06-16 Telefunken Patent Logisches Schaltnetz
US3541543A (en) * 1966-07-25 1970-11-17 Texas Instruments Inc Binary decoder
JPS558135A (en) 1978-07-04 1980-01-21 Mamoru Tanaka Rewritable programable logic array
US4313106A (en) * 1980-06-30 1982-01-26 Rca Corporation Electrically programmable logic array
EP0101884A3 (en) * 1982-07-21 1987-09-02 Hitachi, Ltd. Monolithic semiconductor memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374321A (ja) * 1986-09-18 1988-04-04 Toshiba Corp 書込み可能な論理集積回路
WO1999042928A1 (en) * 1998-02-20 1999-08-26 Sowa Institute Of Technology Co., Ltd. Method of learning binary system
KR100342886B1 (ko) * 1998-02-20 2002-07-04 히로시마 히사야스 이진 시스템 학습 방법
US6611826B1 (en) 1998-02-20 2003-08-26 Sowa Institute Of Technology Co., Ltd. Method of learning binary system

Also Published As

Publication number Publication date
DE3511375A1 (de) 1985-10-17
US4710898A (en) 1987-12-01
DE3511375C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-12-29
DE3546596C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-07-25

Similar Documents

Publication Publication Date Title
US7064579B2 (en) Alterable application specific integrated circuit (ASIC)
KR940010679B1 (ko) 프로그램식 논리 회로를 포함한 집적회로
US7463059B2 (en) Alterable application specific integrated circuit (ASIC)
US4124899A (en) Programmable array logic circuit
JP2548852B2 (ja) プログラマブル論理セル
EP0225715B1 (en) Programmable input/output cell
US5396126A (en) FPGA with distributed switch matrix
JP3539997B2 (ja) 複数の入力を有するルックアップテーブルを実現するために要求されるプログラム可能なアーキテクチャエレメントの数を減じるための方法、およびルックアップテーブルアーキテクチャ
US4783606A (en) Programming circuit for programmable logic array I/O cell
US4551815A (en) Functionally redundant logic network architectures with logic selection means
US6209118B1 (en) Method for modifying an integrated circuit
JPS60204118A (ja) 任意の論理関数を実現する方法及び装置
JP2590110B2 (ja) 書込み可能な論理アレーと同論理アレーをプログラムする方法
US5338982A (en) Programmable logic device
US20080150580A1 (en) Three input field programmable gate array logic circuit configurable as a three input look up table, a d-latch or a d flip- flop
JP2540794B2 (ja) プログラマブルロジツクアレイ回路
JPS6186855A (ja) 出力ロジツク回路
JP2001520812A (ja) 組合されたプログラム可能論理アレーとアレー論理
US5502402A (en) FPGA architecture based on a single configurable logic module
US5039885A (en) Single function programmable logic array circuit
JPS60250712A (ja) デイジタル制御可変周波数発振回路
CA1144608A (en) Programmable array logic circuit
UST956003I4 (en) Interconnect logic for a serial processor
JPS5857825A (ja) Ｐｌａ回路
JPS62269422A (ja) 半導体装置