JPS60198837A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS60198837A
JPS60198837A JP59055612A JP5561284A JPS60198837A JP S60198837 A JPS60198837 A JP S60198837A JP 59055612 A JP59055612 A JP 59055612A JP 5561284 A JP5561284 A JP 5561284A JP S60198837 A JPS60198837 A JP S60198837A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
lead frame
wire
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59055612A
Other languages
English (en)
Inventor
Ikuo Kawamata
川又　郁夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59055612A priority Critical patent/JPS60198837A/ja
Publication of JPS60198837A publication Critical patent/JPS60198837A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は半導体装置にかかり、特にモールド樹脂封止さ
れた半導体装置の耐湿性を向上させる半導体装置の製造
方法に関するものである。
〔従来技術〕
一般にモールド樹脂封入された半導体用パッケージは、
その量産性の良さおよびその低価格のため広く使用され
ている。しかし、他のパッケージ例えばハーメチックク
ールされたセラミックパッケージに比べ、周囲からの水
分や湿気がモールド樹脂中を浸透しやすい。そのため浸
透してきた水分が表面安定用及び表面形状を緩くする絶
縁膜として使用されている不純物含有ガラス、特にリン
珪化ガラス（以下ＰＥＧ膜と称する）と反応してリン酸
となる。このリン酸が配線用金属であるアルミニウムを
溶解してしまい、ついには不良に至る欠点を有し、モー
ルド樹脂封入された半導体用パッケージの耐湿性を低下
させていた。
この不良に対して半導体装置の表面を緻密なパラ７べ一
７ヨン膜（以後、カバー膜と称する）で被うことによυ
外部から浸透してきた水力とＰＥＧ膜を反応させないよ
うな対策が施されてきた。該対策によシカバー膜で被わ
れた部分の耐湿性は向上した。しかし、カバー膜で被う
ことの出来ない部分特に外部引自出し電極部については
アルミニウムが露出しているためモールド樹脂中を浸透
してきた水分等が原因で溶解してしまう問題が依然とし
て残りている。これを第１図および第２図を用いて説明
する。第１図は従来構造に於けるポンディングパッド部
の断面図であシ、１はＰ型半導体基板、２は二酸化シリ
コン膜、３はＰＳＧ膜、４は外部引き出し電極、５はカ
バー膜である。この状態はメタライゼーシ蓼ン後カバー
膜５を形成した段階の断面図である。次に第２図に示す
ように写真蝕刻法によシ外部引出し電極４上にカバー膜
５にケースの内部リードと電気的接続を行うためのスル
ーホールを開孔する。この時、カバー膜のエッチャント
によシ、外部引出し電極４のアルミニウムもニッチ／グ
され、膜厚が薄くなると同時に、ニッチングがアルミニ
ウムのグレインに沿って進み外部引き出し電極４の下の
ＰＳＧ膜３にまで達するピンホール６が開いてしまう。
外部引き出し電極４上にピンホール６が開いた状態で、
モールド樹脂封入技術によシ組み立てられ九半導体装置
は、周囲に存在する水分等がモールド樹脂中を浸透しシ
リコン半導体表面に達し、外部引き出し電極４に開いた
スルーホール６を通Ｊ、ＰＳＧ膜３と反応してしまい、
リン酸となシ、外部引き出し電極４のアルミニウムを溶
解してしまい、ついには半導体装置を不良に到らしめて
しまう耐湿性上の欠陥を有していた。
〔発明の目的〕
本発明は、上記不都合を改善し、しいてはモールド樹脂
封入された半導体装置の耐湿性を向上させる構造を提供
するものである。
〔発明の構成〕
本発明は、リードフレーム上にマウントされた半導体装
置において、リードフレームと半導体装置上に形成され
た外部引き出し用電極とをポンディングワイヤー等で接
続した後、少くとも該半導体装置上に形成された外部引
き出し電極（以下ポンディングパッドと称する）の露出
表面に光已■法によシ、パッシベーション膜を形成する
工程を含むことを特徴とする半導体装置の製造方法であ
る。
〔実施例の説明〕
以下本発明の詳細な説明する。第３図乃至第４図は本発
明一実施例の工程説明図であシ、次にこれ等の図を参照
しつつ説明する。
第３図は通常の方法を用いて、拡散が完了した半導体基
板をダイシングリ−等でペレッタイズを行い、個片にし
た半導体装置を、ペースリボン７に金等のマウント材を
加熱し、半導体基板と金の共晶合金８をつくることによ
シ、マウントし、その後リードフレーム７と半導体装置
上に形成されたポンディングパッド４をポンドイングワ
イヤー９で接続した状態を表すポンディングパッド４部
分の断面図である。この場合ポンディングパッド４はア
ルミニウム、ボンディングワイヤー９は金線である。次
に第４図に示すように、水銀ランプ等を使用した光気相
成長法（以下光ＣＶＤ法と称する）にｇ少くとも該ポン
ディングパッド４の露出表面にバッジベージロン膜ｌＯ
を形成する。
光ＣＶＤ法でバッジベージロン膜１０を形成する方法は
、他の方法例えばシランの７００℃における熱分解によ
る気相成長法に比べ、低温例えば１５０℃でバッジベー
ジ盲ン膜を形成する事が出来るため、パープルグレープ
等によるポンディング強度の低下が起こりにくい従って
高いボンディング強度を有したままでポンディングパッ
ド４の露出表面にパッジベージロン膜１０を形成するこ
とが出来る。この状態では、もはやピンホール６はパッ
シベーション膜ｌＯで被われてしまうためポンディング
パッド部にはＰＳＧ膜３に達するピンホール６は開いて
いない。
〔発明の効果〕
以上説明したように本発明によるモールド樹脂封入半導
体装置は、たとえ外部より水分が浸透してきても水分は
ポンディングパッド部１０において、ＰＥＧ膜と反応出
来ないので、ポンディングパッド４は溶解式れす、耐湿
性のすぐれた半導体装置を得ることが出来る。
【図面の簡単な説明】
第１図及び第２図は従来技術の半導体装置が耐湿性不良
に到る原因を示す断面図であシ、第３図及び第４図は本
発明の実施例を工程順に示す断面図である。 面図に於いて、１・・・・・・Ｐ型半導体基板、２・・
・・・・二酸化シリコン膜、３・・・・・・Ｐ２Ｏ膜、
４・・・・・・ポンディングパッド、５・・・・・・カ
バー膜、６・・・・・・ピンホール、７・・・・・・ベ
ースリボン、８・・・・・・半導体基板と金の共晶合金
、９・・・・・・ボンディングワイヤー、１０・・・・
・・光ＣＶＤ法で形成したパッジベージ璽ン膜である。 第　ｌ　図 憤？図

Claims (1)

    【特許請求の範囲】
  1. リードフレーム上にマウントされた半導体装置において
    、リードフレームと半導体装置上に形成された外部引き
    出し用電極とをボンディングワイヤ等でボンディングし
    た後、少くとも該半導体装置上に形成された外部引き出
    し電極の露出表面に、光ＣＶＤ法により、パッジベージ
    、ン膜を形成する工程を含むことを特徴とする半導体装
    置の製造方法。
JP59055612A 1984-03-23 1984-03-23 半導体装置の製造方法 Pending JPS60198837A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59055612A JPS60198837A (ja) 1984-03-23 1984-03-23 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59055612A JPS60198837A (ja) 1984-03-23 1984-03-23 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS60198837A true JPS60198837A (ja) 1985-10-08

Family

ID=13003585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59055612A Pending JPS60198837A (ja) 1984-03-23 1984-03-23 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60198837A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604556B1 (ko) 2004-10-13 2006-07-28 동부일렉트로닉스 주식회사 반도체 소자의 본딩패드 형성 방법
CN108649018A (zh) * 2018-05-14 2018-10-12 深圳市欧科力科技有限公司 一种功率器件及其封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604556B1 (ko) 2004-10-13 2006-07-28 동부일렉트로닉스 주식회사 반도체 소자의 본딩패드 형성 방법
CN108649018A (zh) * 2018-05-14 2018-10-12 深圳市欧科力科技有限公司 一种功率器件及其封装方法

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