JPS60189561A - メモリアクセス制御方式 - Google Patents

メモリアクセス制御方式

Info

Publication number
JPS60189561A
JPS60189561A JP59045038A JP4503884A JPS60189561A JP S60189561 A JPS60189561 A JP S60189561A JP 59045038 A JP59045038 A JP 59045038A JP 4503884 A JP4503884 A JP 4503884A JP S60189561 A JPS60189561 A JP S60189561A
Authority
JP
Japan
Prior art keywords
memory
address
processor
sub
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59045038A
Other languages
English (en)
Japanese (ja)
Other versions
JPH024936B2 (enrdf_load_stackoverflow
Inventor
Isamu Hasebe
長谷部　勇
Satoru Kitazawa
哲 北澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP59045038A priority Critical patent/JPS60189561A/ja
Publication of JPS60189561A publication Critical patent/JPS60189561A/ja
Publication of JPH024936B2 publication Critical patent/JPH024936B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP59045038A 1984-03-09 1984-03-09 メモリアクセス制御方式 Granted JPS60189561A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59045038A JPS60189561A (ja) 1984-03-09 1984-03-09 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59045038A JPS60189561A (ja) 1984-03-09 1984-03-09 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS60189561A true JPS60189561A (ja) 1985-09-27
JPH024936B2 JPH024936B2 (enrdf_load_stackoverflow) 1990-01-31

Family

ID=12708182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59045038A Granted JPS60189561A (ja) 1984-03-09 1984-03-09 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS60189561A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62295112A (ja) * 1986-06-14 1987-12-22 Mitsubishi Electric Corp 複合制御装置
JPS63239531A (ja) * 1987-03-27 1988-10-05 Nec Corp プログラムロ−ド方式
JPH0312763A (ja) * 1989-06-09 1991-01-21 Fujitsu Ltd Ｉｏプロセッサのイニシアルプログラムロード方式
JP2007077462A (ja) * 2005-09-15 2007-03-29 Gunma Univ ニッケル−リン複合めっき液とその液を使用した複合めっき方法およびその方法を使用した複合めっき部品
JP2010102719A (ja) * 1997-12-17 2010-05-06 Src Computers Inc メモリサブシステムに複数のメモリアルゴリズムプロセッサを組込むマルチプロセッサコンピュータアーキテクチャ
JP2014063510A (ja) * 2013-11-19 2014-04-10 Renesas Electronics Corp データ処理装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5590969B2 (ja) * 2010-06-02 2014-09-17 日立三菱水力株式会社 フランシス型ランナ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124944A (en) * 1977-04-08 1978-10-31 Nec Corp Data processing unit
JPS5650451A (en) * 1979-10-02 1981-05-07 Meidensha Electric Mfg Co Ltd Multiaccess system of multimicrocomputer
JPS56145411A (en) * 1980-04-11 1981-11-12 Panafacom Ltd Program load system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124944A (en) * 1977-04-08 1978-10-31 Nec Corp Data processing unit
JPS5650451A (en) * 1979-10-02 1981-05-07 Meidensha Electric Mfg Co Ltd Multiaccess system of multimicrocomputer
JPS56145411A (en) * 1980-04-11 1981-11-12 Panafacom Ltd Program load system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62295112A (ja) * 1986-06-14 1987-12-22 Mitsubishi Electric Corp 複合制御装置
JPS63239531A (ja) * 1987-03-27 1988-10-05 Nec Corp プログラムロ−ド方式
JPH0312763A (ja) * 1989-06-09 1991-01-21 Fujitsu Ltd Ｉｏプロセッサのイニシアルプログラムロード方式
JP2010102719A (ja) * 1997-12-17 2010-05-06 Src Computers Inc メモリサブシステムに複数のメモリアルゴリズムプロセッサを組込むマルチプロセッサコンピュータアーキテクチャ
JP2007077462A (ja) * 2005-09-15 2007-03-29 Gunma Univ ニッケル−リン複合めっき液とその液を使用した複合めっき方法およびその方法を使用した複合めっき部品
JP2014063510A (ja) * 2013-11-19 2014-04-10 Renesas Electronics Corp データ処理装置

Also Published As

Publication number Publication date
JPH024936B2 (enrdf_load_stackoverflow) 1990-01-31

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