JPS60187963U - Emulation device - Google Patents
Emulation deviceInfo
- Publication number
- JPS60187963U JPS60187963U JP7463184U JP7463184U JPS60187963U JP S60187963 U JPS60187963 U JP S60187963U JP 7463184 U JP7463184 U JP 7463184U JP 7463184 U JP7463184 U JP 7463184U JP S60187963 U JPS60187963 U JP S60187963U
- Authority
- JP
- Japan
- Prior art keywords
- emulation device
- emulation
- instruction sets
- microprocessor
- recorded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例に係るエミュレーシヨン装置
の構成を示すブロック図、第2図は実施例におけるエミ
ュレーション部4内の表示回路の構成を示すブロック図
、第3図はマイクロプロセッサ5から出力されるシステ
ムクロックCL、アドレス/ステータス信号AS、スト
ローブ信号STのタイミング図である。
1・・・管理部、2・・・メモリ、3・・・ブレーク制
御部、4・・・エミュレーション部、5・・・マイクロ
プロセッサ、6・・・ラッチ回路、7・・・バッファ、
8・・・LED、9・・・抵抗、10・・・電源接続用
端子、AS・・・アドレス/ステータス信号、ST・・
・ストローブ信号、CL・・・システムクロック、A・
・・アドレス信号、S・・・ステータス信号。FIG. 1 is a block diagram showing the configuration of an emulation device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a display circuit in the emulation section 4 in the embodiment, and FIG. FIG. 3 is a timing diagram of a system clock CL, an address/status signal AS, and a strobe signal ST outputted from the FIG. DESCRIPTION OF SYMBOLS 1... Management part, 2... Memory, 3... Break control part, 4... Emulation part, 5... Microprocessor, 6... Latch circuit, 7... Buffer,
8...LED, 9...Resistor, 10...Power supply connection terminal, AS...Address/status signal, ST...
・Strobe signal, CL...system clock, A.
...Address signal, S...Status signal.
Claims (1)
レーションを行なうエミュレーション装置において、 前記マイクロブ町セッサの複数の命令セットのうちいず
れの命令セットをエミュレーション中であるかを表示す
る手段を有することを特徴とするエミュレーション装置
。[Claims for Utility Model Registration] In an emulation device that emulates a microprocessor having a plurality of instruction sets, means for displaying which instruction set is being emulated among the plurality of instruction sets of the micro processor. An emulation device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7463184U JPS60187963U (en) | 1984-05-22 | 1984-05-22 | Emulation device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7463184U JPS60187963U (en) | 1984-05-22 | 1984-05-22 | Emulation device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60187963U true JPS60187963U (en) | 1985-12-12 |
Family
ID=30615107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7463184U Pending JPS60187963U (en) | 1984-05-22 | 1984-05-22 | Emulation device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60187963U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5510628A (en) * | 1978-07-07 | 1980-01-25 | Toshiba Corp | Object program display system |
JPS5835647A (en) * | 1981-08-27 | 1983-03-02 | Nec Corp | Appreciating device for microcomputer |
-
1984
- 1984-05-22 JP JP7463184U patent/JPS60187963U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5510628A (en) * | 1978-07-07 | 1980-01-25 | Toshiba Corp | Object program display system |
JPS5835647A (en) * | 1981-08-27 | 1983-03-02 | Nec Corp | Appreciating device for microcomputer |
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