JPS5835647A - Appreciating device for microcomputer - Google Patents

Abstract

PURPOSE:To prevent an erroneous appreciation, by providing a device type selecting means in an appreciating device and informing it to the external, when an instruction which is not permitted, is read. CONSTITUTION:A host processor 1 reads contents of a device selecting switch 16 and stores them in a working area on a host memory 2. The start address of an invalid instruction set table corresponding to contents of the working area is set to a table pointer in the working area. The processor 1 reads one-instruction components of code from a paper tape reader 3 and extracts the operation code part from contents of them and stores it in the working area. The processor 1 refers to the invalid instruction set table designated by the table pointer; and if the instruction coincident with contents of the working area is detected, the output indicating that the invalid instruction is inputted is outputted to a console 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer evaluation device, and more particularly, to a microcomputer evaluation device that can evaluate all models of a microcomputer family having a plurality of models each consisting of a subset under one instruction system and architecture. This invention relates to a microcomputer evaluation device that can be evaluated.

In recent years, advances in semiconductor technology have made it possible to obtain large quantities of inexpensive microcomputers.The types of microcomputers range from so-called multi-chip microcomputers with external memory, to single-chip microcomputers with built-in memory. Microcomputers are diversifying. Normally, a single-chip microcomputer stores the program code A in an internal ROM (read-only memory), so an evaluation device that allows the contents of the program memory to be rewritten at the stage of creating the program is required. used.

In addition, l-chip microco/pinter t”tlil
- architecture - and instruction system,
It is common to have multiple models with configurations most suitable for the field of application. These microcomputers having the same architecture and instruction system are said to constitute one family. Each model within a family may have, for example, a different amount of data memory, program memory, or a different number of human output ports, but the total number of instructions available for use also usually differs accordingly. It is. Further, even if the instruction operations and the total number of codes are not different, the size of data that can be written in the operand part of an instruction is different from the general VC.

Therefore, an evaluation device should be prepared for each model even if the models are in the same family. This is because if the number of instructions for model A is 50 and the number of instructions for model B is 47, then an evaluation device to evaluate both of these must be able to execute at least 50 instructions. Comment 11 [1i] When I went to gold, B made a mistake and AK was not punched, and even if I used the allowed command, AK would still work without any problems, so the evaluation result of 7 would be incorrect. It is.

Especially in a one-chip microcomviator using a program memory KROMt, this type of evaluation error can cause great damage to the user. This is because in a 1-chip microcomputer, ROMti
It is normal for the data to be written at the semiconductor manufacturer, and after it has been overwritten, to the time the sample is delivered to you, it will drop within one month or two or three months at the most, but this type of error occurs on the evaluation equipment.

Even if the chip is working normally, it will not work on the actual chip, so it will have to be rewritten after obtaining the sample, which will delay the development period by up to three months.

Despite the drawbacks mentioned above, currently microcomputers of the same family are evaluated by one evaluation device mainly for economic reasons, so it is possible to completely eliminate the above-mentioned erroneous evaluations. Things were impossible.

The present invention provides an evaluation device with a model selection means for selecting a model within a family, and when a program is loaded into the evaluation device, it is determined whether instructions used in the program are allowed for the selected model. The purpose of this is to prevent the above-mentioned erroneous evaluations by providing a means to notify external parties if an unacceptable command is read. be.

How does each model of the microcomputer family operate according to the invention? An emulator for emulating, a program storage means for storing instructions to be executed by the Emmy V-Y, a program loading means for loading a program into the program storage means, and a plurality of @ buildings of the microcomputer family. and means for detecting an instruction that cannot be used on the model selected by the model selection means from among the programs loaded by the program loading means and outputting a message to that effect. A micro combinatorial evaluation device is obtained.

The present invention will be described in detail below with reference to the drawings.

Figure 1 is a block diagram of one implementation of the present invention, in which 1 is a host processor, 2 is a host memory, 3 is a paper tape reader, 4 is a console, 5 to 8 Vi buffers, and 9 is a program. Memory, 10 emulate, 11
is the RUN signal, 12 is the A bus%, 13 is the D bus, 14 is the A' path, 15 is the I bus, and the host processor 1, which is a 16-digit model selection switch, inputs data from the Gio tape reader 3 and the console 4. It is also possible to output data using the 3V console. The host memory 2 contains instructions (host program) 21 to be executed by the host processor 1 and the host processor l.
The illegal command table 22 for each model of emulator IO placed in ll'F is stored and retrieved.

Also, host memory 21j:, host processor 1
A working area is also secured.

5 of 16 host processor IFi model selection switches
By determining tl-a<, the emulator 10 determines which model of the microcomputer family it should emulate. When the RUN signal 11 output from the host processor I is at a high level, the emulator lO outputs the address information of the program to be executed to the A' bus 4 to the program memory 9 via the buffer 7, and commands corresponding to the address. instruction bus 1 via buffer 8
Read from 5 and execute the command. Buffers 7 and 8
9 is conductive only when the RUN signal 11 is at a high level.
．． When the RUN signal is low, their outputs are in a high impedance state.

By lowering the RUN signal 11 to the base, the host processor 1 can stop execution of the emulator 10 instructions and change the contents of the program memory 9 via buffers 5 and 6. .

Buffers 5 and 6 are opposite vcR to buffers 7 and 8.
When the UN signal is at a low level, it becomes a conductive leech, and when it is still at a high level, it becomes a high impedance.

Next, a specific method of detecting an instruction that is not allowed for a specified model, which is the object of the present invention, will be explained with reference to FIGS. 1 and 2.

FIG. 2 is a flowchart of a program to be executed by the host processor l of FIG.

First, the host processor l reads the contents of the horizontal 1 selection switch 16 and stores the contents in 8WK of the working area on the host memory 2. Then, the start address of the illegal instruction set table corresponding to the contents of SW is stored in the table port (TP) in the working area.
Set K.

Next, the host processor l receives the code 1kiIll! for one instruction from the paper tape reader 3! The contents are stored in IN5T on the working area, and the (7) OPCODE part is extracted and stored in MOP on the working area. Next, the illegal instruction set table specified by the host processor IUTP is indexed to see if there is a match with the contents of the MOP, and if there is a match,
An output indicating that an illegal command has been input is output to the console 4. If there is no match, the contents of %lN5T are stored in the program memory 9, and reading of the command from the paper tape reader 3 is resumed.

As explained above, according to the present invention, if an instruction that is not allowed to be used is loaded into the program memory, it can be detected immediately before it is loaded. It is no longer possible to incorrectly evaluate the equipment correctly, and therefore the problem of delays in development time as described above is eliminated, and development is completed at the expected time. It is also economical because all models can be evaluated by simply switching the model selection switch using the same evaluation vIclt.

In the above embodiment, an illegal instruction set table is used in the host memory 2, but this is because the number of illegal instructions is generally smaller than the number of matching instructions. In the above, a legal instruction set table is provided instead of an illegal instruction set table, and the one that matches the operating W/ code of the read instruction is considered a legal instruction set.
It may be possible to inform the outside that an illegal command has been input in the table.

In addition, as a model selection means, a model selection switch is used in the actual m column above, but for this purpose, a model identification code is punched at the beginning of the paper tape where the instructions are punched, and the host processor There is nothing wrong with a method that recognizes the model when you first load it.

Additionally, if there is an instruction that cannot be determined to be legal or illegal based on the Operation 11 code alone, it can be detected by storing information such as the range of operands in the illegal (or legal) instruction table. If you are a good person, you will easily understand this.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a flow diagram showing a program to be executed by the host processor 2 of FIG. l...Host processor, 2...Host memory, 3...--Paper tape reader% 4
...'3/sole, 5~8-*-/<sofa,
9...Program memory, 10...
Emulator, 11...RUN signal, 12...
...A bus%13...-, D bus, 14...
...AI Babasu 15...I Bus, 16...
...Model selection switch.

Claims (1)

[Claims] an emulator that emulates the operation of each model of the microcomputer family; a program storage means that stores instructions to be executed by the emulator; a program load means that loads the entire program into the program storage means; and the microcomputer. - a model selection means for selecting one of the plurality of models in the family; and a model selection means from among the programs loaded by the program loading means]! ! A micro combinatorial evaluation device characterized by having means for detecting an instruction that cannot be used in a selected model and outputting a message to that effect.