JPS60180167A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60180167A JPS60180167A JP3435484A JP3435484A JPS60180167A JP S60180167 A JPS60180167 A JP S60180167A JP 3435484 A JP3435484 A JP 3435484A JP 3435484 A JP3435484 A JP 3435484A JP S60180167 A JPS60180167 A JP S60180167A
- Authority
- JP
- Japan
- Prior art keywords
- impurity layer
- type impurity
- conduction type
- conductivity type
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は半導体装置の製造方法、詳しくは、すぐれた
耐圧特性を有するＭＯＳ ＦＥＴの製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS FET having excellent breakdown voltage characteristics.
（従来技術）
従来の高耐圧ＭＯ８ＦＥＴ の製造方法を第１図を参照
して説明する。(Prior Art) A conventional method for manufacturing a high voltage MO8FET will be explained with reference to FIG.
まず、Ｐ型シリコン基板１の所定の領域に、イオン打込
みおよび高温熱処理によりＰ＋型不純物層２を形成する
。次に、前記と同領域にＮ型の不純物をイオン打込み法
で注入して、熱処理を行うことによシ、前記Ｐ＋型不純
物層２の表面側の濃度を低下させ、この部分ｔ−Ｐ一層
３とする。（第１図（ａ））この後、ソース・ドレイン
としてのＮ型不純物層４．５を形成する。その場合、ド
レインとしてのＮ型不純物層５は、前記Ｐ＋型不純物層
２から所定距離離間した基板部表面に形成される。一方
、ソースとしてのＮ型不純物層４は、前記Ｐ＋型不純物
層２上に（Ｐ一層３に）前記ドレインとしてのＮ型不純
物層５と反対側において形成される。（第１図Φ））
しかる後、Ｎ型不純物層４側において前記Ｎ型不純物層
５と隣接する基板部にＮ一層６、つまシ、Ｎ型不純物層
５と同一導電型の低濃度の領域を形成する。（第１図（
Ｃ））
その後、Ｖ層６とＮ型不純物層４間の基板上にゲート絶
縁膜７を形成し、その上にはゲート電極８を形成する。First, a P+ type impurity layer 2 is formed in a predetermined region of a P type silicon substrate 1 by ion implantation and high temperature heat treatment. Next, by implanting an N-type impurity into the same region as described above by ion implantation and performing heat treatment, the concentration on the surface side of the P+ type impurity layer 2 is lowered, and this portion t-P becomes even thicker. Set it to 3. (FIG. 1(a)) After this, an N-type impurity layer 4.5 as a source/drain is formed. In that case, the N-type impurity layer 5 as a drain is formed on the surface of the substrate portion separated from the P+ type impurity layer 2 by a predetermined distance. On the other hand, an N-type impurity layer 4 serving as a source is formed on the P+ type impurity layer 2 (on the P layer 3) on the opposite side from the N-type impurity layer 5 serving as the drain. (Fig. 1 Φ)) After that, on the N-type impurity layer 4 side, a low concentration region of the same conductivity type as the N-type impurity layer 5 is formed in the substrate portion adjacent to the N-type impurity layer 5. form. (Figure 1 (
C)) Thereafter, a gate insulating film 7 is formed on the substrate between the V layer 6 and the N-type impurity layer 4, and a gate electrode 8 is formed thereon.
さらに、ソース・ドレインとしてのＮ型不純物層４，５
に接続してソース電極９、ドレイン電極１０’に形成す
る。（第１図（ｄ））このようにして製造されたＭＯＳ
ＦＥＴ においては、Ｎ一層６が、ドレインとしての
Ｎ型不純物層５とゲート電極８の間にあってピンチオフ
領域となるため、いわゆるオフセットゲート型の構造と
なっている。このため、高い耐圧特性を示す。Furthermore, N-type impurity layers 4 and 5 as sources and drains
The source electrode 9 and the drain electrode 10' are connected to the source electrode 9 and the drain electrode 10'. (Figure 1(d)) MOS manufactured in this way
In the FET, the N layer 6 is located between the N-type impurity layer 5 as a drain and the gate electrode 8 and serves as a pinch-off region, so that it has a so-called offset gate type structure. Therefore, it exhibits high breakdown voltage characteristics.
さらに、ゲート絶縁膜７の下にＰ＋型不純物層２がある
ため、ブレークダウン時、ゲート端で発生した正孔電流
は低抵抗のＰ＋型不純物層２を通ってソースとしてのＮ
型不純物層４に流れる。このため、ゲートバイアスの発
生が小さく、負性抵抗現象による耐圧降下は小さくなっ
ている。Furthermore, since there is a P+ type impurity layer 2 under the gate insulating film 7, the hole current generated at the gate end at the time of breakdown passes through the low resistance P+ type impurity layer 2 and is transferred to N as a source.
It flows into the type impurity layer 4. Therefore, the occurrence of gate bias is small, and the breakdown voltage drop due to the negative resistance phenomenon is small.
しかるに、上述した従来の方法では、ピンチオフ領域と
なるＮ一層６と、ブレークダウン時、ゲート端で発生し
た電流を流す低抵抗部であるＰ型不純物層２の２つを別
々に作らねば々らず、しかも、Ｐ＋型不純物層２の形成
に、Ｐ＋層の形成と、その一部をＰ”−４とする工程を
必要とし、工程が繁雑になる欠点があった。However, in the conventional method described above, it is necessary to separately create two layers: the N layer 6, which serves as a pinch-off region, and the P-type impurity layer 2, which serves as a low-resistance portion through which the current generated at the gate end flows during breakdown. Moreover, the formation of the P+ type impurity layer 2 requires a step of forming a P+ layer and converting a part of it to P''-4, which has the disadvantage of making the process complicated.
（発明の目的）
この発明は上記の点に鑑みなされたもので、その目的は
、工程簡単にして高耐圧のＭＯＳ ＦＥＴを製造できる
半導体装置の製造方法を提供することにある。(Objective of the Invention) The present invention has been made in view of the above points, and its object is to provide a method for manufacturing a semiconductor device that can manufacture a high voltage MOS FET with a simple process.
（発明の概要）
この発明の要点は、半導体基板表面上の絶縁膜に、ソー
ス・ドレインとしての一対の不純物層間において、さら
には前記一方の不純物層上に大きく延在して開口部を形
成し、その開口部を通して一導電型の不純物を基板部に
イオン注入し熱処理することにより、ピンチオフ領域と
、ブレークダウン時、ゲート端で発生した電流を流す低
抵抗部とを同時に形成することにある。(Summary of the Invention) The key point of the present invention is to form an opening in an insulating film on the surface of a semiconductor substrate, between a pair of impurity layers serving as a source and a drain, and further extending widely over one of the impurity layers. By implanting ions of impurities of one conductivity type into the substrate through the opening and heat-treating the substrate, a pinch-off region and a low-resistance region through which current generated at the gate end flows during breakdown are simultaneously formed.
（実施例） 以下この発明の一実施例を第２図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
第２図（ａ）において、２１は（１００）結晶軸、２〜
５Ω・ｍのＰ型のシリコン基板（半導体基板）であシ、
まず、この基板２１上に酸化膜２２を形成する。次に、
その酸化膜２２にホトリソ工程で開口部２３．２４’ｅ
形成した後、その開口部２３゜２４を用いて拡散技術に
よシ、ソース・ドレインとしての一対のＮ型不純物層（
逆導電型不純物層）２５．２６を基板２１表面部に形成
する。（第２図（ａ））
しかる後、酸化処理を行って、前記開口部２３゜２４を
埋めるように酸化膜を成長させることによシ、前記基板
２１上の酸化膜をほぼ均一な厚さく ５０００〜１００
００Ｘ厚）の酸化膜（絶縁＠）２７とする。次いで、こ
の酸化膜２７にホトリソ工程で開口部２８を形成する。In Fig. 2(a), 21 is the (100) crystal axis, 2~
5Ω・m P-type silicon substrate (semiconductor substrate),
First, an oxide film 22 is formed on this substrate 21. next,
Openings 23.24'e are formed in the oxide film 22 by a photolithography process.
After forming, a pair of N-type impurity layers (as source and drain) are formed using the openings 23 and 24 by diffusion technology.
Opposite conductivity type impurity layers 25 and 26 are formed on the surface of the substrate 21. (FIG. 2(a)) Thereafter, an oxidation treatment is performed to grow an oxide film so as to fill the openings 23 and 24, thereby making the oxide film on the substrate 21 approximately uniform in thickness. 5000~100
An oxide film (insulating@) 27 with a thickness of 00X is used. Next, an opening 28 is formed in this oxide film 27 by a photolithography process.
この開口部２８は、前記一対のＮ型不純物層２５．２６
間のゲート領域において、さらにはドレインとしての一
方のＮ型不純物層２６上に大きく（１０〜１５μｍ長の
Ｎ型不純物層２６に対して２〜５μｍ位）延在して形成
される。その後、比較的低温、例えば８００℃で酸化処
理を行う。すると、前記開口部２８により露出したゲー
ト領域の基板部表面に３０ＯＡ厚程度のゲート部酸化膜
２９が形成される。同時に、同じく前記開口部２８によ
り露出したＮ型不純物層２６の表面部にドレイン開口部
酸化膜３０が形成されるが、Ｎ型不純物層２６は不純物
が高濃度に拡散されているため、ドレイン開口部酸化膜
３０は、低温酸化においては、５００〜８００λ厚の厚
い膜となる。（第２図伽））
その後、基板２１と同一導電型の不純物であるＰ型不純
物３１例えばボロンを、開口部２８より酸化膜２９．３
０’！＆通して基板２１中にイオン注入法で打込む。こ
の時、ゲート部酸化膜２９下の基板部に打込まれたＰ型
不純物３１は、ゲート部敵化膜２９が薄いため深い濃度
プロファイルを示す。一方、ドレイン開口部酸化膜３０
下のドレインとしてのＮ型不純物層２６中に打込まれた
Ｐ型不純物３１は、ドレイン開口部酸化膜３０が厚いた
め浅い濃度プロファイルを示す。勿論、この時の打込み
電圧および濃度は、５０〜１００ｖ程度の耐圧特性によ
り適当な値に設定される必要がある。（第２図（Ｃ））
次に、９００℃、６０〜９０分程度の熱処理を０２豚囲
気中で行う。すると、前記打込まれたＰ型不純物３１が
活性化され、ソース・ドレインとしての一対のＮ型不純
物層２５．２６間の基板部にＰ＋型不純物層（高濃度不
純物層）３２が形成される。同時に、このＰ型不純物層
３２と隣接する前記ドレインとしてのＮ型不純物層２６
の一部が、その部分に打込まれたＰ型不純物３１により
Ｎ〜層（低濃度不純物層）３３となる。さらに、他部に
比較しでは薄い酸化膜２９．３０の部分の厚さが増して
全体がほぼ均一な厚さとなるように基板２１上に酸化膜
３４が形成される。しかる後、酸化膜３４に、Ｐ壓不純
物層３２上のゲート領域において開口部３５を形成し、
それにより露出したＰ＋型不純物層３２の表面部にゲー
ト絶縁膜３６を形成する。次いで、任意のスレッショル
ド電圧（例えば１．０〜１．５ Ｖ ）を得るため、Ｎ
型不純物３７例えばリンまたはヒ素などを前記ゲート絶
縁膜３６を介してＰ型不純物層３２の表面部に打込む。This opening 28 is formed by the pair of N-type impurity layers 25 and 26.
In the gate region between them, it is formed to extend greatly (approximately 2 to 5 μm with respect to the N type impurity layer 26 having a length of 10 to 15 μm) on one of the N type impurity layers 26 serving as a drain. Thereafter, oxidation treatment is performed at a relatively low temperature, for example, 800°C. Then, a gate oxide film 29 having a thickness of about 30 OA is formed on the substrate surface of the gate region exposed through the opening 28. At the same time, a drain opening oxide film 30 is formed on the surface of the N-type impurity layer 26 exposed by the opening 28, but since the N-type impurity layer 26 has impurities diffused at a high concentration, the drain opening The partial oxide film 30 becomes a thick film with a thickness of 500 to 800λ in low-temperature oxidation. (Fig. 2)) Then, a P-type impurity 31, such as boron, which is an impurity of the same conductivity type as the substrate 21, is added to the oxide film 29.3 through the opening 28.
0'! & is implanted into the substrate 21 by ion implantation. At this time, the P-type impurity 31 implanted into the substrate below the gate oxide film 29 exhibits a deep concentration profile because the gate oxide film 29 is thin. On the other hand, the drain opening oxide film 30
The P-type impurity 31 implanted into the N-type impurity layer 26 serving as the lower drain exhibits a shallow concentration profile because the drain opening oxide film 30 is thick. Of course, the implantation voltage and concentration at this time need to be set to appropriate values based on the withstand voltage characteristics of about 50 to 100V. (FIG. 2(C)) Next, heat treatment is performed at 900° C. for about 60 to 90 minutes in the 02 pig enclosure. Then, the implanted P type impurity 31 is activated, and a P+ type impurity layer (high concentration impurity layer) 32 is formed in the substrate portion between the pair of N type impurity layers 25 and 26 serving as the source and drain. . At the same time, the N-type impurity layer 26 as the drain adjacent to this P-type impurity layer 32
A part of the layer becomes an N~ layer (low concentration impurity layer) 33 due to the P type impurity 31 implanted into that part. Further, the oxide film 34 is formed on the substrate 21 so that the thickness of the oxide film 29, 30, which is thinner than other parts, is increased so that the entire thickness becomes substantially uniform. Thereafter, an opening 35 is formed in the oxide film 34 in the gate region above the P impurity layer 32,
A gate insulating film 36 is formed on the surface portion of the P+ type impurity layer 32 exposed thereby. Then, to obtain an arbitrary threshold voltage (e.g. 1.0-1.5 V), N
A type impurity 37, such as phosphorus or arsenic, is implanted into the surface of the P-type impurity layer 32 through the gate insulating film 36.
（第２図（ｄ））
そして、その打込み後、熱処理して前記Ｎ型不純物３７
を活性化させることによｐ、チャンネル用Ｐ−不純物層
３８をＰ＋型不純物層３２の表面部に得る。しかる後、
ソース争ドレインコンタクト孔を前記酸化膜３４に形成
した上でソース電極３９゜ドレイン電極４０、さらには
ゲート電極４１を形成する。（第２図（ｅ））
以上で高耐圧ＭＯ８ＦＥＴ が完成する。なお、この例
はＮチャンネル高耐圧ＭＯＳ ＦＥＴ の場合であるが
、各部の導電型をすべて逆にして同様にしてＰチャンネ
ル高耐圧ＭＯＳ ＦＥＴ ’ｅ製造することができる。(FIG. 2(d)) After the implantation, heat treatment is performed to form the N-type impurity 37.
By activating P, a channel P- impurity layer 38 is obtained on the surface of the P+ type impurity layer 32. After that,
After forming source and drain contact holes in the oxide film 34, a source electrode 39, a drain electrode 40, and a gate electrode 41 are formed. (Figure 2(e)) With the above steps, the high voltage MO8FET is completed. Although this example is for an N-channel high-voltage MOS FET, a P-channel high-voltage MOS FET can be manufactured in the same manner by reversing the conductivity type of each part.
（発明の効果）
以上の一実施例から明らかなように、この発明の方法で
は、半導体基板表面上の絶縁膜に、ソース・ドレインと
しての一対の不純物層間において、さらには前記一方の
不純物層上の一部に延在して開口部を形成した後、その
開口部を通して一導電型の不純物を基板部にイオン注入
し熱処理することによシ、ピンチオフ領域となる低濃度
不純物層と、ブレークダウン時、ドレインのゲート端で
発生した電流を流す低抵抗部としての高濃度不純物層と
を同時に形成することができる。したがって、高耐圧の
ＭＯＳ ＦＥＴ ’を比較的簡単にして製造できる。(Effects of the Invention) As is clear from the above embodiment, in the method of the present invention, the insulating film on the surface of the semiconductor substrate is coated between a pair of impurity layers serving as a source and a drain, and furthermore, After forming an opening extending over a part of the substrate, an impurity of one conductivity type is ion-implanted into the substrate through the opening and heat-treated to form a low-concentration impurity layer that will become a pinch-off region and break down. At the same time, a high-concentration impurity layer can be formed at the same time as a low-resistance portion through which current generated at the gate end of the drain flows. Therefore, a high voltage MOS FET' can be manufactured relatively easily.
第１図は従来の高耐圧ＭＯ８ＦＥＴ の製造方法を示す
断面図、第２図はこの発明の半導体装置の製造方法の一
実施例１を示す断面図である。
２１・・・シリコン基板、２５．２６・・・Ｎ型不純物
層、２７・・・酸化膜、２８・・・開口部、３１・・・
Ｐ型不純物、３２・・・Ｐ＋型不純物層、３３・・・ｒ
層。
特許出願人 沖電気工業株式会社FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a high voltage MO8FET, and FIG. 2 is a cross-sectional view showing a first embodiment of the method for manufacturing a semiconductor device according to the present invention. 21... Silicon substrate, 25. 26... N-type impurity layer, 27... Oxide film, 28... Opening, 31...
P type impurity, 32...P+ type impurity layer, 33...r
layer. Patent applicant Oki Electric Industry Co., Ltd.
Claims (1)
の一対の逆導電型不純物層を形成する工程と、その後、
前記半導体基板表面上の絶縁膜に前記一対の不純物層間
において、さらには前記一方の不純物層上の一部に延在
して開口部を形成する工程と、その開口部を介して一導
電型の不純物を基板部にイオン注入した後、熱処理する
ことにより、前記一対の逆導電型不純物層間の基板部に
一導電型の高濃度不純物層を形成すると同時に、この高
濃度不純物層と隣接する前記一方の逆導電型不純物層の
一部分を逆導電型の低濃度不純物層とする工程とを具備
することを特徴とする半導体装置の製造方法。A step of forming a pair of opposite conductivity type impurity layers as a source and drain on the surface of a semiconductor substrate of one conductivity type, and then
forming an opening in the insulating film on the surface of the semiconductor substrate between the pair of impurity layers and further extending over a part of the one impurity layer; After ion-implanting impurities into the substrate portion, heat treatment is performed to form a high concentration impurity layer of one conductivity type in the substrate portion between the pair of opposite conductivity type impurity layers, and at the same time, to form a high concentration impurity layer of one conductivity type in the substrate portion between the pair of opposite conductivity type impurity layers, and at the same time, to form a high concentration impurity layer of one conductivity type in the substrate portion between the pair of opposite conductivity type impurity layers A method of manufacturing a semiconductor device, comprising the step of: forming a part of the opposite conductivity type impurity layer into a reverse conductivity type low concentration impurity layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3435484A JPS60180167A (en) | 1984-02-27 | 1984-02-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3435484A JPS60180167A (en) | 1984-02-27 | 1984-02-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60180167A true JPS60180167A (en) | 1985-09-13 |
Family
ID=12411811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3435484A Pending JPS60180167A (en) | 1984-02-27 | 1984-02-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60180167A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060033A (en) * | 1988-08-18 | 1991-10-22 | Seiko Epson Corporation | Semiconductor device and method of producing semiconductor device |
-
1984
- 1984-02-27 JP JP3435484A patent/JPS60180167A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060033A (en) * | 1988-08-18 | 1991-10-22 | Seiko Epson Corporation | Semiconductor device and method of producing semiconductor device |
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