JPH0316140A - Manufacture of mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process by a method wherein, before a polysilicon film is oxidized and after it has been oxidized, a low-concentration ion implantation process and a high-concentration ion implantation process are executed respectively. CONSTITUTION:For example, phosphorus ions are implanted into a p-type silicon substrate 11 by making use of a polysilicon film 14 to be used as a gate electrode as a mask; an n-type low-concentration diffusion layer 15 is formed. For example, arsenic ions are implanted into the p-type silicon substrate 11 by making use of an oxide layer 16 of a polysilicon film as a mask; an n-type high-concentration diffusion layer 17 is formed. In this manner, the polysilicon film 14 to be used as the gate electrode is used as the impurity implantation mask when a source-drain diffusion layer is formed; a low-concentration ion implantation process and a high-concentration ion implantation process are executed respectively before the polysilicon film 14 is oxidized and after it has been oxidized. As a result, when only an oxidation process is executed during an ion implantation operation, the source-drain diffusion layer can be formed in a self-aligned manner. Thereby, a manufacturing process can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device.

2. Description of the Related Art In recent years, MOS type semiconductor devices have come into widespread use due to the demand for low power consumption. On the other hand, as the degree of integration of integrated circuits increases, there is a need to reduce the size of semiconductor devices, but as the gate length of MOS semiconductor devices decreases, the punch-through breakdown voltage of P-channel transistors increases. In addition, it is known that in N-channel transistors, the electric field strength near the drain region increases and hot carriers are generated, resulting in a so-called short channel effect that significantly lowers the threshold voltage.

In order to suppress these short channel effects,
There is a method of providing a low concentration diffusion layer in the source/drain region at the end on the gate side, such as a source/drain double diffusion structure known as an LDD structure.

A conventional method for manufacturing a MOS type semiconductor device will be described below, taking the structure of an N-channel transistor as an example.

FIGS. 4(a) to 4(d) are step-by-step cross-sectional views of a part of a conventional method for manufacturing a MOS type semiconductor device, in which 1 is p-type silicon, 2 is an element isolation region, 3 is a gate oxide film, and 4 is a 5 is an n-type low concentration diffusion layer, 7 is an n-type high concentration diffusion layer, and 8 is a silicon oxide film.

First, an element isolation region 2 made of a thick oxide film is formed on a p-type silicon substrate 1 using a known technique. Next, a gate oxide film 3 is grown on the p-type silicon substrate 1, and a polysilicon film 4 that will become a gate electrode is elongated thereon. Then,
Highly concentrated phosphorus is diffused into the polysilicon film 4 in a vapor phase to form a low resistance film. Further, a resist film is formed into a desired resist pattern using an exposure technique, and using this resist pattern as a mask, the polyrecon film 4 is selectively removed by dry etching to form a gate electrode, and then the resist is removed. The state at this time is shown in FIG. 4 (al).

Next, as shown in FIG. 4(b), a low concentration impurity is implanted into the p type silicon substrate 1 using the polysilicon film 4 serving as the gate electrode as a mask to form an n type low concentration diffusion layer 5.

Next, as shown in FIG.
The silicon oxide film 8 is grown to a thickness of , and anisotropic etching is performed so that the silicon oxide film 8 remains only on the side edges of the gate electrode, thereby forming a substrate.

Then, as shown in FIG. 4 (dl), the polysilicon film 4
Then, high concentration impurities are implanted into the p-type silicon substrate 1 using the spacer of the silicon oxide film 8 as a mask to form an n-type high concentration diffusion layer 7, and a source/drain double diffusion layer is formed at both ends of the gate electrode. do.

Problems to be Solved by the Invention However, in the above-mentioned conventional method for manufacturing a MOS type semiconductor device, in order to form a source/drain double diffusion layer at both ends of a gate electrode, a silicon oxide growth process and a silicon oxide growth process are required. This method requires an etching process to form the spacer, resulting in an increase in manufacturing costs. Furthermore, since it is necessary to control the spacer length with high precision, there is also the problem that the process becomes complicated. Furthermore, after forming the source/drain low-concentration diffusion layer, the dimensions of the gate are reduced due to the oxidation process of the polysilicon film that will become the gate electrode. There is also the problem that the transistor becomes a so-called offset transistor in which the source and drain do not overlap, and the electrical characteristics of the transistor change significantly.

An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that can easily form double diffusion layers for the source and drain of the MOS type semiconductor device while reducing the number of manufacturing steps.

Means for Solving the Problems The method for manufacturing a MOS type semiconductor device of the present invention involves implanting low concentration impurities into a silicon substrate using a polysilicon film, which is a gate electrode implanted with high concentration impurities, as a mask, and then oxidizing the silicon substrate. After growing an oxide layer on the surface of the polysilicon film to form a substrate on both ends of the gate electrode,
Using the oxide layer of this polysilicon film as a mask, high concentration impurities are implanted into the silicon substrate.

Alternatively, high concentration impurities are implanted into the silicon substrate using the polysilicon film that is implanted with high concentration impurities as a gate electrode as a mask, and then the surface of the polysilicon film that is the gate electrode is oxidized, and then the polysilicon film is oxidized. After removing the layer, a low concentration impurity is implanted into the silicon substrate using the polysilicon film that will become the gate electrode as a mask.

Alternatively, after oxidizing the polysilicon film that is the gate electrode into which the high concentration impurity J has been introduced, the high concentration impurity is implanted into the silicon substrate in a self-aligned manner using the oxide layer of the polysilicon film as a mask. Next, the oxide layer of the polysilicon film is removed, and then low concentration impurities are implanted into the silicon substrate using the polysilicon film that will become the gate electrode as a mask.

Effect: According to the method of the present invention, enhanced oxidation is used in which the polysilicon film that is the gate electrode is oxidized at a faster oxidation rate than the silicon substrate because it is diffused with high concentration impurities.
Using the polysilicon film that is the gate electrode as a mask, low-concentration impurities are implanted into the silicon substrate, and the polysilicon film is further oxidized to form an oxide layer of polysilicon film that will serve as a spacer on both ends of the gate electrode. Using the oxide layer of the film as a mask, source/drain double diffusion layers can be formed in a self-aligned manner.

Alternatively, high-concentration impurities are implanted into the silicon substrate using the polysilicon film that is the gate electrode as a mask, and the polysilicon film is further oxidized to form an oxide layer of the polysilicon film that will serve as a spacer at both ends of the gate electrode. By removing the oxide layer of the polysilicon film, the polysilicon film, which has dimensions smaller than when implanting high-concentration impurities, is used as a mask to implant low-concentration impurities into the silicon substrate in a self-aligned manner, resulting in double diffusion of the source and drain. The layers can be formed in a self-aligned manner.

Alternatively, oxidize the polysilicon film that is the gate electrode,
An oxide layer of polysilicon film that will serve as a spacer is formed on both ends of the gate electrode, and high-concentration impurities are implanted into the silicon substrate using this oxide layer of polysilicon film as a mask.Furthermore, an oxide layer of polysilicon film is formed to remove the spacer. is removed, and then low concentration impurities are implanted into the silicon substrate using the polysilicon film as a mask, thereby forming source/drain double diffusion layers in a self-aligned manner.

In other words, although the process is simple and does not require the silicon oxide film lengthening or selective silicon oxide film removal steps as in the conventional example, the source... A MOS type semiconductor device having a drain double diffusion layer can be obtained.

EXAMPLE Hereinafter, a method for manufacturing a MOS type semiconductor device according to the present invention will be explained with reference to the drawings. Here, three embodiments will be described for the case of an N-channel transistor.

1 to 3 are step-by-step cross-sectional views showing a part of the method for manufacturing a MOS type semiconductor device of the present invention.

In FIGS. 1 to 3, 11 is a p-type silicon substrate;
2 is an element isolation region, 13 is a gate oxide film, 14 is a polysilicon film, 15 is an n-type low concentration diffusion layer, 16 is an oxide layer of the polysilicon film, and 17 is an n-type high concentration diffusion layer.

First, a first example will be described using FIG. 1.

For example, an element isolation region 12 made of a thick oxide film is formed on a p-type silicon substrate 11 having a concentration of 5 x 10 l6 am-3 using a known technique. Next, p-type silicon substrate 1
1, a gate oxide film 13 is grown to a thickness of, for example, 10 nm, and a polysilicon film 14 that will become a gate electrode is grown thereon to a thickness of, for example, 0.4 μm. Next, high-concentration phosphorus is vapor-phase diffused into the polysilicon film 14 at, for example, 1000° C. to form a low-resistance film with a concentration of, for example, 3×10-20aI1-3. Furthermore, a resist film was spin-coated, the resist film was formed into a desired resist pattern using exposure technology, and using this resist pattern as a mask, the polysilicon film 14 was selectively removed by dry etching to form a gate electrode. After that, remove the resist. The state at this time is shown in FIG. 1(a).

Next, as shown in FIG. 1(b), using the polysilicon film 14 serving as the gate electrode as a mask, for example, phosphorus ions are applied to the p-type silicon substrate 11 at 60 k e V, 1.
The n-type low concentration diffusion layer 15 is formed by implantation under the conditions of 0 x 10 l3am-2 (low concentration ion implantation step).

Next, as shown in Fig. 1 fcl, for example, 900°C,
Polysilicon film 14 is thermally oxidized for 30 minutes.

As a result, an oxidized layer 16 of the polysilicon film having a thickness of, for example, 0.2 μm is formed on the surface of the polysilicon film 14 by accelerated oxidation. That is, by elongating the oxide layer l6 of the polysilicon film, a source/drain implantation mask with a 0.1 μm spacing on one side is formed. At this time,
Gate oxide film 13 not covered with polysilicon film 14
The thickness of the layer increases to, for example, 40 nm by thermal oxidation (
oxidation process).

Next, as shown in FIG.
-2 conditions to form an n-type high concentration diffusion layer 17 (high concentration ion implantation step).

Through the above steps, source/drain double diffusion layers are formed at both ends of the gate electrode. Furthermore, an annealing process is performed at 1000° C. for 20 minutes so that the n-type low concentration diffusion layer 15 overlaps the polysilicon film 14 serving as the gate electrode.
5 diffusion length can be controlled.

Thereafter, an N-channel transistor is formed using a known technique.

According to the manufacturing method of such a MOS type semiconductor device, a polysilicon film that will become a gate electrode is used as an impurity implantation mask when forming double diffusion layers of the source and drain, and low Since a concentrated ion implantation process and a high concentration ion implantation process are performed, the source/drain double diffusion layer can be formed in a self-aligned manner by simply providing an oxidation process during ion implantation, simplifying the manufacturing process. Therefore, it is possible to obtain a highly accurate and inexpensive MOS type semiconductor device with little variation.

Next, a second embodiment will be described using FIG. 2.

First, an element isolation region 12 made of a thick oxide film is formed on a p-type silicon substrate 11 having a concentration of, for example, 5 x 10 l6c+n-3 using a known technique. Next, a gate oxide film 13 is grown on the p-type silicon substrate 11 to a thickness of, for example, 10 nm, and a polysilicon film 14 that will become a gate electrode is grown thereon to a thickness of, for example, 0.4 μm. Then,
Highly concentrated phosphorus is applied to the polysilicon film 14 at, for example, 1000°C.
For example, at a concentration of 3' X I Q 2 0
It is a low resistance film of am-3. Furthermore, a resist film is spin-coated, the resist film is formed into a desired resist pattern using exposure technology, and using this resist pattern as a mask, the polysilicon film 14 is selectively removed by dry etching to form a gate electrode. After that, remove the resist.

The state at this time is shown in FIG. 2 ta+.

Next, as shown in FIG. 2 (bl), using the polysilicon film 14 serving as the gate electrode as a mask, arsenic ions, for example, are applied to the p-type silicon substrate 11 at 40 k e V, 4X.
The n-type high concentration diffusion layer 17 is implanted under the condition of 10'5α-2.
(high concentration ion implantation process).

Next, as shown in Figure 2 (Cl), for example, at 900°C,
Polysilicon film 14 is thermally oxidized for 30 minutes. As a result, an oxide layer 16 of a polysilicon film having a thickness of, for example, 0.2 μm is formed on the surface of the polysilicon lI 14 by accelerated oxidation. At this time, the thickness of the gate oxide film 13 not covered with the polysilicon film 14 is reduced by thermal oxidation to, for example, 4.
Elongate to 0 nm (oxidation process).

Next, as shown in FIG. 2 (dl), the oxide layer 16 of the polysilicon film is removed by, for example, etching treatment using a mixed solution of hydrogen fluoride and ammonium fluoride (oxide layer removal step), and then the gate electrode is etched. Using a certain polysilicon film 14 as a mask, for example, phosphorus ions are applied to the p-type silicon substrate 11 at 5 9 k e V, 1 0 x 1 013a.
The n-type low concentration diffusion layer 5 is formed by implantation under the condition of r+-2 (low concentration ion implantation step).

Through the above steps, source/drain double diffusion layers are formed at both ends of the gate electrode.

Thereafter, an N-channel transistor is formed using a known technique.

In the manufacturing method of the MOS type semiconductor device formed as described above, a polysilicon film that will become the gate electrode is used as an impurity implantation mask when forming the source/drain double diffusion layer, and a high concentration Ion implantation is performed, and low concentration ion implantation is performed after polysilicon oxidation and removal of the oxide layer, so it is a good idea to have an oxidation process and an oxide layer removal process that can be controlled with high precision during ion implantation. A double diffusion layer for the drain can be formed in a self-aligned manner. Furthermore, since the polysilicon film that will become the gate electrode after the oxide film is removed is used as a mask to implant impurities to form low concentration diffusion layers for the source and drain, it is possible to ensure the overlap between the gate and the source and drain. The process can be simplified, and a highly accurate and inexpensive MOS semiconductor device with little variation can be obtained.

Next, a third embodiment will be described using FIG. 3.

First, for example, p with a concentration of 5 x 10 l6 cm-3
An element isolation region 12 made of a thick oxide film is formed on a mold silicon substrate 11 using a known technique. Next, a gate oxide film 13 is grown to a thickness of, for example, 10 nm on the p-type silicon substrate 11, and a polysilicon film 13 that will become the gate electrode is placed on top of the gate oxide film 13.
4 is grown to a thickness of, for example, 0.4 μm. Next, high-concentration phosphorus is vapor-phase diffused into the polysilicon film 14 at, for example, 1000° C. to form a low-resistance film with a concentration of, for example, 3×1020 cm −3 . Furthermore, a resist film is spin-coated, the resist film is formed into a desired resist pattern using exposure technology, and using this resist pattern as a mask, the polysilicon film 14 is selectively removed by dry etching to form a gate electrode. After that, remove the resist.

The state at this time is shown in FIG. 3 (al).

Next, as shown in FIG. 3(b), for example, at 900°C,
Polysilicon film 14 is thermally oxidized for 30 minutes. As a result, an oxidized layer 16 of a polysilicon film having a thickness of, for example, 0.2 μm is formed on the surface of the polysilicon film 14 by accelerated oxidation. That is, by elongating the oxide layer 16 of the polysilicon film, a source/drain implantation mask with a 0.1 μm spacer added to one side is formed. At this time, the thickness of the gate oxide film 13 not covered with the polysilicon film l4 is increased to, for example, 40 nm by thermal oxidation (oxidation step).

Next, as shown in FIG. 3 (Cl), using the oxide layer 16 of the polysilicon film as a mask, arsenic ions, for example, are implanted into the p-type silicon substrate 11 under conditions of 40 keV and 4xIQ"cm-2 to form an n-type The high concentration diffusion layer 17 is shaped (high concentration ion implantation step).

Next, as shown in FIG. 3 (d+), after the oxide layer 16 of the polysilicon film is removed by etching using a mixed solution of hydrogen fluoride and ammonium fluoride (oxide layer removal step), the gate electrode is removed. A certain polysilicon film 1
4 as a mask, for example, phosphorus ions are applied to the p-type silicon substrate 11 at 60 k e V, 10 x 101
The n-type low concentration diffusion layer 15 is formed by implantation under the condition of 3cra-2 (low concentration ion implantation step).

Through the above steps, source/drain double diffusion layers are formed at both ends of the gate electrode.

Thereafter, an N-channel transistor is formed using a known technique.

In the manufacturing method of the MOS type semiconductor device formed as described above, a polysilicon film that will become the gate electrode is used as an impurity implantation mask when forming the source/drain double diffusion layer, and the polysilicon film is oxidized and the oxide layer is removed. Since a high-concentration ion implantation process and a low-concentration ion implantation process are performed later, the double diffusion layers of the source and drain can be formed in a self-aligned manner by simply performing the ion implantation & oxidation process and the oxide layer removal process. Furthermore, since the polysilicon film that will become the gate electrode after the oxide film is removed is used as a mask to implant impurities to form low concentration diffusion layers for the source and drain, it is possible to ensure overlap between the gate and the source and drain. Therefore, the manufacturing process can be simplified, and a highly accurate and inexpensive MOS type semiconductor device with little variation can be obtained.

Effects of the Invention According to the method for manufacturing a MOS type semiconductor device of the present invention, a polysilicon film that will become a gate electrode is used as an impurity implantation mask when forming double diffusion layers for source and drain, and Since a low-concentration ion implantation process and a high-concentration ion implantation process are performed later, the source/drain double diffusion layer can be formed in a self-aligned manner by simply providing an oxidation process during ion implantation, or The polysilicon film that will become the gate electrode is used as an impurity implantation mask when forming the source/drain double diffusion layer, and high-concentration ion implantation is performed before polysilicon oxidation, and low-concentration ion implantation is performed after polysilicon oxidation and oxide layer removal. In order to perform ion implantation, the source/drain double diffusion layer can be formed in a self-aligned manner by simply providing an oxidation step and an oxide layer removal step that can be controlled with high precision during ion implantation. Furthermore, since the polysilicon film that will become the gate electrode after the oxide film is removed is used as a mask to implant impurities to form low concentration diffusion layers for the source and drain, it is possible to ensure overlap between the gate and the source and drain. The polysilicon film that will become the gate electrode is used as an impurity implantation mask when forming the source/drain double diffusion layer, and a high-concentration ion implantation process and a low-concentration ion implantation process are performed after oxidizing the polysilicon film and removing the oxide layer, respectively. Therefore, by simply performing an oxidation process and an oxide layer removal process during ion implantation, a double diffusion layer for the source and drain can be formed in a self-aligned manner, and furthermore, it can become the gate electrode after the oxide film is removed. Since the impurity implantation for forming the source/drain low concentration diffusion layer is performed using the polysilicon film as a mask, it is possible to ensure overlap between the gate and the source/drain, which simplifies the manufacturing process.
A highly accurate and inexpensive MOS type semiconductor device with little variation can be obtained.

[Brief explanation of the drawing]

FIG. 1 (a+ to +d) is a step-by-step sectional view showing a method for manufacturing a MOS type semiconductor device according to a first embodiment of the present invention;
FIG. 2 +al to fdl are step-by-step cross-sectional views showing a method for manufacturing a MOS type semiconductor device according to a second embodiment of the present invention;
FIGS. 3(a) to 3(dl) are step-by-step cross-sectional views showing a method for manufacturing a MOS type semiconductor device according to a third embodiment of the present invention;
FIG. 4 (al~(di is MO in the conventional embodiment)
1A and 1B are step-by-step cross-sectional views showing a method for manufacturing an S-type semiconductor device. 1...p-type silicon substrate, 2...element isolation region, 3...gate oxide film, 4...
・Polysilicon film, 5... n-type low concentration diffusion layer,
6...Oxide layer of polyrecon film, 7...
・N-type high concentration diffusion layer.

Claims (3)

[Claims] (1) When forming the source/drain double diffusion layer of a MOS type semiconductor device, low concentration impurities are applied to the silicon substrate using a polysilicon film formed on the silicon substrate via a gate oxide film and serving as a gate electrode as a mask. a low concentration ion implantation step of forming a low concentration diffusion layer by implanting; an oxidation step of oxidizing the surface of the polysilicon film after the low concentration ion implantation step; A high concentration ion implantation step of forming a high concentration diffusion layer in a self-aligned manner by implanting high concentration impurities into the silicon substrate using the polysilicon film as a mask, and determining the diffusion length of the low concentration diffusion layer. A method for manufacturing a MOS type semiconductor device, comprising a controlled annealing step. (2) When forming the source/drain double diffusion layer of a MOS type semiconductor device, high concentration impurities are applied to the silicon substrate using the polysilicon film formed on the silicon substrate via the gate oxide film and serving as the gate electrode as a mask. a high concentration ion implantation step of forming a high concentration diffusion layer by implanting, an oxidation step of oxidizing the surface of the polysilicon film after the high concentration ion implantation step, and then removing the oxidized layer of the polysilicon film. an oxide layer removal step; and a low concentration ion implantation step of forming a low concentration diffusion layer in a self-aligned manner by injecting low concentration impurities into the silicon substrate using the polysilicon film as a mask after removing the oxide layer. A method for manufacturing a MOS type semiconductor device. (3) When forming a source/drain double diffusion layer of a MOS type semiconductor device, an oxidation process of oxidizing the surface of a polysilicon film that is formed on a silicon substrate via a gate oxide film and becomes a gate electrode; A high concentration ion implantation step of forming a high concentration diffusion layer by implanting high concentration impurities into the silicon substrate using the polysilicon film oxidized by the oxidation step as a mask, and then removing the oxidized layer of the polysilicon film. an oxide layer removal step; and a low concentration ion implantation step of forming a low concentration diffusion layer in a self-aligned manner by injecting low concentration impurities into the silicon substrate using the polysilicon film as a mask after removing the oxide layer. A method for manufacturing a MOS type semiconductor device.