JPS60180050U

JPS60180050U - Common bus line occupancy control device

Info

Publication number: JPS60180050U
Application number: JP5862485U
Authority: JP
Inventors: 純一小室
Original assignee: カシオ計算機株式会社
Priority date: 1985-04-18
Filing date: 1985-04-18
Publication date: 1985-11-29

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例のシステム構成図、第２図
はコントローラ４の詳細な構成図、第３図はプロセッサ
１〜３のサイクリックな優先順位を示す図、第４図はこ
の実施例の各種事例を説明する図である。１〜３・・・プロセッサ、４・・・コントローラ、５・
・・コモンＲＡＭ、６〜８・・・シーケンス制御回路、
６Ａ〜８Ａ・・・ネクストシーケンス制御ゲート、６Ｂ
〜８Ｂ・・・ネクストシーケンス制御フリップフロップ
、１２〜１４・・・トリガバスバッファゲート回路、Ａ
Ｂｉ　ＤＢ・・・共通パスライン。補正　昭６０．５．１７　　　−− 考案の名称を次のように補正する。 ■考案の名称　　共通パスライン占有制御装置−１実用
新案登ｉ請求の範囲、図面の簡単な説明を次のように補
正する。　　− ０実用新案登録請求のｉ囲すからのリクエスト信号を所定の優先　位に従つ、　　
　　ｍ番　（１≦ｍ≦ｎ　のプロセッサがバスライる手
段と、ｍ＋１番目（ただしｍ＝ｎのときは１番目）のプ
ロセッサの優先順位を最上位に設定する手段とを具備し
たことを特徴とする共通パスライＺ貞４１枦即」１図面の簡単な説明第１図はこの考案の一実施例のシステム構成図、第２Ｕ
ＩｊＪはコントローラ４の詳細な構成図、第　　　−３
図はプロセッサ１〜３のサイクリックな優先順位を示す
図、第４図はこの実施例の各種事例を説明する図である
。。１〜３・・・プロセッサ、４・・・コントローラ、５・
・・コモンＲＡＭ、６〜８・・・シーケンス制御回路、
６Ａ〜８Ａ・・・ネクストシーケンス制御ゲート、６Ｂ
〜８Ｂ・・・ネタストシーケクス制御フリップフロップ
、１２〜１４・・・トリガバスバッファゲート回　　　
−路、ＡＢ、ＤＢ・・・共通パスライン。FIG. 1 is a system configuration diagram of an embodiment of this invention, FIG. 2 is a detailed configuration diagram of the controller 4, FIG. 3 is a diagram showing the cyclic priority order of processors 1 to 3, and FIG. It is a figure explaining various examples of an example. 1 to 3...processor, 4...controller, 5.
...Common RAM, 6-8...Sequence control circuit,
6A to 8A...Next sequence control gate, 6B
~8B...Next sequence control flip-flop, 12-14...Trigger bus buffer gate circuit, A
Bi DB...Common pass line. Amendment May 17, 1980 -- The name of the invention is amended as follows. ■Name of the invention Common pass line occupancy control device-1 Utility model registration i The scope of the claims and the brief description of the drawings are amended as follows. - following the request signals from the i box of the utility model registration request according to a predetermined priority;
The present invention is characterized by comprising a means for the m-th processor (1≦m≦n) to ride the bus, and a means for setting the priority of the m+1-th (however, the first when m=n) processor to the highest priority. 1 Brief explanation of the drawings Figure 1 is a system configuration diagram of an embodiment of this invention, and the 2nd U
IjJ is a detailed configuration diagram of the controller 4, No.-3
The figure shows the cyclic priorities of processors 1 to 3, and FIG. 4 is a diagram explaining various examples of this embodiment. . 1 to 3...processor, 4...controller, 5.
...Common RAM, 6-8...Sequence control circuit,
6A to 8A...Next sequence control gate, 6B
~8B... Netast sequence control flip-flop, 12-14... Trigger bus buffer gate circuit
- path, AB, DB...common path line.

Claims

[Scope of utility model registration request]

In a computer system having a plurality of processors, each of which is connected to a shared device via a common path line, and which selectively executes processing for the shared device with a predetermined priority, two or more Means for recognizing the processor that had occupied the shared device until immediately before and setting the priority of the processor to the lowest level when occupancy requests are made from the processors to the shared device at the same time; A common path line occupancy control device comprising: means for executing priority control of the shared device according to the priority order of the common path line occupancy control device.