JPS60178566A - アクセス制御方式 - Google Patents

アクセス制御方式

Info

Publication number
JPS60178566A
JPS60178566A JP3496484A JP3496484A JPS60178566A JP S60178566 A JPS60178566 A JP S60178566A JP 3496484 A JP3496484 A JP 3496484A JP 3496484 A JP3496484 A JP 3496484A JP S60178566 A JPS60178566 A JP S60178566A
Authority
JP
Japan
Prior art keywords
access
control
priority
determination circuit
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3496484A
Other languages
English (en)
Japanese (ja)
Other versions
JPH022178B2 (enrdf_load_stackoverflow
Inventor
Hidehiko Nishida
西田 秀彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3496484A priority Critical patent/JPS60178566A/ja
Priority to CA000469910A priority patent/CA1221464A/en
Priority to EP84402614A priority patent/EP0147295B1/en
Priority to US06/682,316 priority patent/US4718006A/en
Priority to DE8484402614T priority patent/DE3484235D1/de
Priority to AU36857/84A priority patent/AU554059B2/en
Priority to KR1019840008243A priority patent/KR890004995B1/ko
Priority to BR8406678A priority patent/BR8406678A/pt
Priority to ES539033A priority patent/ES539033A0/es
Publication of JPS60178566A publication Critical patent/JPS60178566A/ja
Publication of JPH022178B2 publication Critical patent/JPH022178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657Access to multiple memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
JP3496484A 1983-12-26 1984-02-25 アクセス制御方式 Granted JPS60178566A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP3496484A JPS60178566A (ja) 1984-02-25 1984-02-25 アクセス制御方式
CA000469910A CA1221464A (en) 1983-12-26 1984-12-12 Data processor system having improved data throughput of multiprocessor system
EP84402614A EP0147295B1 (en) 1983-12-26 1984-12-17 Data processing system including a plurality of multiprocessor systems
US06/682,316 US4718006A (en) 1983-12-26 1984-12-17 Data processor system having improved data throughput in a multiprocessor system
DE8484402614T DE3484235D1 (de) 1983-12-26 1984-12-17 Datenverarbeitungssystem mit mehreren multiprozessorsystemen.
AU36857/84A AU554059B2 (en) 1983-12-26 1984-12-18 A data processor system having improved data throughput of multiprocessor system
KR1019840008243A KR890004995B1 (ko) 1983-12-26 1984-12-21 멀티프로세서 시스템의 향상된 데이타 처리능력을 갖는 데이타 처리시스템 및 방법
BR8406678A BR8406678A (pt) 1983-12-26 1984-12-21 Sistema processador de dados incluindo uma pluralidade de sistemas multiprocessadores e processo para processamento de dados em uma unidade de controle de memoria fornecida em um sistema multiprocessador
ES539033A ES539033A0 (es) 1983-12-26 1984-12-24 Una instalacion de tratamiento de datos que incluye una pluralidad de dispositivos multiprocesadores.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3496484A JPS60178566A (ja) 1984-02-25 1984-02-25 アクセス制御方式

Publications (2)

Publication Number Publication Date
JPS60178566A true JPS60178566A (ja) 1985-09-12
JPH022178B2 JPH022178B2 (enrdf_load_stackoverflow) 1990-01-17

Family

ID=12428825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3496484A Granted JPS60178566A (ja) 1983-12-26 1984-02-25 アクセス制御方式

Country Status (1)

Country Link
JP (1) JPS60178566A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63284660A (ja) * 1987-05-16 1988-11-21 Nec Corp プロセッサ間通信方式
JP2006221433A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置
JP2006221432A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63284660A (ja) * 1987-05-16 1988-11-21 Nec Corp プロセッサ間通信方式
JP2006221433A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置
JP2006221432A (ja) * 2005-02-10 2006-08-24 Sony Corp 共有メモリ装置

Also Published As

Publication number Publication date
JPH022178B2 (enrdf_load_stackoverflow) 1990-01-17

Similar Documents

Publication Publication Date Title
US6078983A (en) Multiprocessor system having distinct data bus and address bus arbiters
US5136500A (en) Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories
KR890004995B1 (ko) 멀티프로세서 시스템의 향상된 데이타 처리능력을 갖는 데이타 처리시스템 및 방법
JPH0479026B2 (enrdf_load_stackoverflow)
JPS60178566A (ja) アクセス制御方式
JP2684793B2 (ja) 情報処理装置
JPH0341856B2 (enrdf_load_stackoverflow)
JPH05282242A (ja) バス制御方式
JPH0715670B2 (ja) デ−タ処理装置
JP2640104B2 (ja) データ転送装置
JPS61165144A (ja) メモリアクセス制御方式
JP2972568B2 (ja) バス拡張装置
JPS59173864A (ja) 主記憶制御方式
JPS6116115B2 (enrdf_load_stackoverflow)
JPS61143863A (ja) バス分割制御方式
JPS63259746A (ja) バンクメモリ間のデ−タ転送方式
JPH04256056A (ja) コンピュータシステム
JPS60137157A (ja) 相互通信機構と隣接通信機構を有するデ−タ処理装置
JPH04236651A (ja) バス制御方式
JPH0423159A (ja) 共有メモリ装置
JPH0690711B2 (ja) メモリアクセス制御方式
JPS62187956A (ja) Dma制御方式
JPH0561839A (ja) データ転送装置
JPH02125358A (ja) 多重バスメモリアクセス調停方式
JPH0553975A (ja) バス制御装置